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AM6526: camera interface

ajayt
Genius 9555 points

Part Number: AM6526

Another question about the camera interface on the AM65x. 

 

  1. We are confused by the formula for setting the BYSoutput port pixel clock (see CAL_BYS_CTRL1 register field BC1_PCLK) it seems wrong to us. It doesn’t produce a sensible answer. We are wondering if the formula should be 2^16*PCLK/FCLK? This to us would make more sense because it would express a normalised value of how many FCLK cycles you need to wait before the state machine updates.
  2. Also can Ti confirm where to find the BYSout port in the CAL block. We cannot find it on any diagram. We can see the BYS input port but not the BYS output port.

 

  • 0
    TI__Mastermind 23125 points

    Ajayt, 

    BYSout port is not used in AM65. Thus only CAL_BYS_CTRL1[31] BYSINEN shall be used, which enables BYSinput port if parallel or non-CSI LVDS camera input is used. Rest of the fields in the register controls timing parameters of BYSout port, where you should leave BC1_PCLK=0 to save power. The formula as shown in the description is correct, though it is irrelevant. 

    The original CAL IP contains a BYS module, which has one input and one output port. The BYSoutput port also generate video timing signals. That was how the register was defined.  

    Descriptions under Figure 12-3395 may give you more details about how to setup ports inside CAL based on which camera source is used. let me know if you have further questions. 

    regards

    Jian