DDR2 address pins question (dm6467t)

Brandy Jabkiewicz

Hello,

I want to use a 512 DDR but it uses 14 row address bits. Right now the EVM uses 256mB with settings = 8 banks, 1024 page size, 13 address bits according to the data sheet (http://www.elpida.com/eolpdfs/E1173E40_EOL.pdf). I see that there is a pin for a 14th address bit connected on the EVM, but I guess it is not used.

I would like to use the 14th bit. My concern is that there is this line in the sprueq4d.pdf (http://focus.ti.com/lit/ug/sprueq4d/sprueq4d.pdf) that says it only supports 13 row address bits. From the quote, I cannot understand how the driver will know that it has 512mB available to it. If I set my bank size to 8 and my page to 1024, how can I tell it to recognize the 14th row address bit. Please clarify.

Section 2.6 - "The DDR2 memory controller logical address always contains 13 row address bits, whereas the number of

column and bank bits are determined by the IBANK and PAGESIZE fields."

Thanks,

Brandy

over 14 years ago

0 srirami over 14 years ago

TI__Expert 8260 points

Brandy,

I am looking at this. I will get back to as soon as I have answer for this.

Regards, Srirami.

0 srirami over 14 years ago in reply to srirami

TI__Expert 8260 points

Brandy,

When you say, you want to use 512MB DDR2, I assume you will be using two 2Gbit (256MB) DDR2 parts, like on DM6467 EVM (Page 14 in DM6467 schematic: http://support.spectrumdigital.com/boards/evmdm6467/revf/Schematics/DaVinciHD_EVM_Schematics_RevF.pdf). If that's case, the 14 DDR2 address lines (DDR_A[0:13]) are sufficient. For example, in the attached Micron 1Gbit (128MB) and 2Gbit (256MB), the difference is only A13, which is available on DM6467.

Regards, Srirami.

Micron_DDR2_Parts.zip

0 Brandy Jabkiewicz over 14 years ago in reply to srirami

Mastermind 6325 points

Yes, I think that is exactly what we want to do. I am only concerned that the user guide does not match the behavior. The user guide says it only supports 13 row address bits (meaning A0 to A12). Is this a typo then?

Thanks,

Brandy

0 srirami over 14 years ago in reply to Brandy Jabkiewicz

TI__Expert 8260 points

Brandy,

Yes, its a typo in the user's guide. Thanks for catching it. It will be taken care in the next revisino of the document.

Regards, Srirami.

0 Bhavin Patel over 14 years ago in reply to srirami

Prodigy 180 points

Hello Srirami,

I am using two 2Gbit (256MB) DDR2 parts with DM6467 as discussed in this email chain (http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/t/96523.aspx)

I can see that there is a typo in DDR2 controller user guide. To use 14 raw address bits, what should be my DDR2 controller configuration (SDBCR register)?

Thanks,

Bhavin

0 Bhavin Patel over 14 years ago in reply to Bhavin Patel

Prodigy 180 points

Hello,

Can somebody please reply?

I am looking for DM6467 DDR2 controller settings (SDBCR register) to use two 256MB DDR.

Thanks,

Bhavin

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DDR2 address pins question (dm6467t)