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TDA4VM: Ethernet CML connection - SGMII 2.5Gbpbs

Stefan_Haas
Mastermind 25212 points
Part Number: TDA4VM

on behalf of a customer: 

Hello, 

I need to connect ethernet PHY using HISGMII (2.5 SGMII) which IO operating in CML (current mode logic) with TDA4VM embedded switch (LVDS?)

As I understood only TX path need additional 100ohm differential termination.

 

Q&A:

1.to which J7 voltage domain should I connect "LVDS receiver supply" ?

2. is there need to place additional capacitors on TX/RX  signal lines ?

 

Thanks, Stefan

  • 0
    TI__Expert 6965 points

    1. All J7 SERDES signaling is supported by VDD_PHYIO_1V8 power rail connected to SoC's VDDA_1P8_SERDES0_1 & VDDA_1P8_SERDES2_3 voltage domains.

    2. Please find below J7 CML & LVDS interface routing guidance:

    • TX path (LVDS to CML): 
    • Use 100 Ohm differential termination, located near the LVDS device.  (Note this could already be included in the terminating peripheral).
    • Use AC coupling caps (e.g., 4.7nF)  (4.7nF was mentioned because that value is used by PCIe Gen1, which runs at about the same frequency.)
    • RX path (CML to LVDS):
    • Inputs on SoC have the 100 Ohm differential RX termination present, so it is not needed on the board.
    • AC couple the RX path (same value as in TX path).