TDA4VM: Processors forum

BenM

Part Number: TDA4VM

Hello I am trying to get 3 separate SGMII Phys working on SerDes4. in PSDK 7.0. To start I am only trying to get a single phy working. After updating board_serdes_cgf.c to use SerDes4:

serdesLane0EnableParams.serdesInstance = (CSL_SerdesInstance) 4;

serdesLane0EnableParams.baseAddr = CSL_SERDES_10G0_BASE;

The application crashes a few lines later in CSL_serdesPorReset()

void CSL_serdesPorReset(uint32_t baseAddr) //modified for sierra wiz
{

CpswAppUtils_print("In %s %s\n",__FILE__,__FUNCTION__);//this one
CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(baseAddr + 0x404),31,31, 0x1);

CSL_serdesCycleDelay(1000);

CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(baseAddr + 0x404),31,31, 0x0);
}

Questions:

1. Has SGMII on Serdes4 been tested with this software?

2. The register that is being accessed above (0x50500000 + 0x404) is not in the TRM. I cannot find it for the other SerDes either. Is there any documentation of these registers? Any idea what needs to be done to avoid this crash? Perhaps something needs to be clocked or powered on?

3. The Phys that I am integrating with are 1 lane SGMII (1rx,1tx). How do I set this parameter? Do I use 3 and then adjust the mask for each phy?

serdesLane0EnableParams.numLanes = 0x2;

serdesLane0EnableParams.laneMask = 0x3;

Thanks,

Ben

over 5 years ago

0 Vineet Roy over 5 years ago

TI__Mastermind 37435 points

Hi Ben,

Which guide are you referring to for PHY integration ?

Can you take a look at this page as a reference ? If you haven't done so already.

CPSW provides a reference PHY driver for SGMII in VSC8514 QSGMII PHY driver.

We can take a look at your questions once you have had a chance to go through it.

Also, can I recommend that you migrate to SDK 7.1 as it more mature ?

Regards

Vineet

0 BenM over 5 years ago in reply to Vineet Roy

Expert 2220 points

Hi Vineet,

We are using the DP83867 which has an existing driver, we just need to add SGMII support for it. The application is crashing before even attempting to configure the phy. It is crashing while trying to set up SGMII on SERDES 4 (10G). All of the example code uses SERDES0 which is 16G. When setting up line rates and other configuration the code takes a different path with SERDES4 (also referred to as TORRENT in the code).

Can you comment more specifically what the undocumented register is doing (0x50500000 + 0x404)? Porting forward to 7.1 may not be an option for our customer, so I would like to know more specifically if you think it is supported. Perhaps the subsystem is not powered or clocked?

Thanks,

Ben

0 Vineet Roy over 5 years ago in reply to BenM

TI__Mastermind 37435 points

Hi Ben,

I will forward this to the Ethernet expert

Regards

Vineet

0 Vineet Roy over 5 years ago in reply to Vineet Roy

TI__Mastermind 37435 points

Hi Ben,

Can you post your entire code for initialization for faster debug ? If it's NDA then please reach out via the TI representative and we can do it over email.

Regards

Vineet

0 Prasad Jondhale over 5 years ago in reply to Vineet Roy

TI__Mastermind 27743 points

Hi Ben,

Closing this thread as debugging on dedicated WebEx. We can update this thread with a summary once the debug is closed.