66AK2H14: XFI at 1p25G

Bruno B

Part Number: 66AK2H14

Hi,

I am currently experimenting a very simple setup relative to XFI at 10Gb/s loopback :

This lab is OK and I am able to run all the 3 "serdes_diag" tools : "serdes_diag_PRBS", "serdes_diag_EyeDiagram" , and "serdes_diag_BER' .Everything is fine there.

My problem when I try to change the datarate from 10G to 1.25G.

To do so I have modified the "serdes_diag_platform.h" file - for datarate itself (1p25G), and for lane rate as well (QUARTER_RATE) -

My new configuration; which I think is in accordance with the table11-1 from SPRUHO3A document, is the following :

These updates do not seem to be enough because none of the 3 serdes_diag tools is no more able to run till the end. All 3 tools are looping waiting for "CSL_SERDES_STATUS_PLL_LOCKED' ( function "CSL_Serdes_Deassert_Reset" from 'CSL_serdes2.h" file)

I also notice that (after pausing the SOC under CCS910 while looping) that the register "LANExCTL_STS" is not initialized in accordance to table 11-1 of SPRUHO3A requiring "Bit_width"=10 while this field appears to be equal to 16 bits.(same for Rx and Tx sides)

==> I am wondering if this functionality (running XFI at 1,25G) , normally supported by CSL (this is written in the SPRUHO3A) is really supported and tested . Is there any other parameter to change in order to downgrade the 10Gb datarate to 1,25Gb datarate ?

I also noticed some incoherency between CSL and SPRUHO3A in the loop waiting for "CSL_SERDES_STATUS_PLL_LOCKED" :

- On one hand the software is pooling COMLANE_1F8( bits30..29) while the SPRUHO3A gives the flags at location bit29, and bit28.

- On the other hand the flag from COMLANE_1F8 is identified as a Lane_OK status, not a PLL_OK status.

MAy be I am missing something again.

==> What is this flag signification ? lane ? or PLL ?

With best regards,

Bruno

over 4 years ago

0 auppu6547 over 4 years ago

TI__Expert 3795 points

Bruno,

The link_rate looks correct but can set the lane_rate back to full_rate? XFI uses PHY-B serdes where it uses a 1.25G PLL at full rate. (SGMII uses PHY-A where it uses a 5G PLL and you need to set it to quarter rate for 1.25G)

bits 30 and 29 are the correct lanes for a 2 lane PHY. XFI is a 2 lane PHY where the lane 0 uses "lane 1" and lane 1 uses "lane 2" according to documentation. Some of the code polls for LANE_OK directly since PLL_OK is a prerequisite for LANE_OK.

Regards,

Arun

0 Aravind Batni over 4 years ago in reply to auppu6547

TI__Expert 8885 points

Bruno,

Can you please comment if the response from Arun is good for you to close this thread? Is there any other questions?

Thanks,

0 Bruno B over 4 years ago in reply to Aravind Batni

Expert 1290 points

Hi Arun,

Sorry for the delay.

First information that I did not tell you in my fist post : the PRBS was type 7
- When changing to 31 changes the behaviour : the test ends , but without detecting PRBS.

2nd information after changing LANE_RATE to FULL instead of QUARTER ( and keeping PRBS31 generation) :

==> The result is still not satisfactory : no PRBS detected.

==> This is also the same in QUARTER_MODE (and PRBS31)

nota : If I return back to 10p3125G and FULL Rate, then PRBS31 re-goes detected.

With best regards

Bruno

0 Aravind Batni over 4 years ago in reply to Bruno B

TI__Expert 8885 points

Hi Bruno,

I will ask Arun to take a look on this.

Please note that I am on time bank for next 2 wks. So, please expect delay in my response.

0 Aravind Batni over 4 years ago in reply to Aravind Batni

TI__Expert 8885 points

Hi Bruno,

Sorry for the delay. I am still not able to close this with Arun..

Wondering if you are still having this issue or you got pass this issue?

Please let me know.

0 Bruno B over 4 years ago in reply to Aravind Batni

Expert 1290 points

Hi Aravind,

Since there are many other things to check I stopped the experimentation on this problem, waiting for your answer...

0 Aravind Batni over 4 years ago in reply to Bruno B

TI__Expert 8885 points

Hi Bruno,

Thanks for the update. I will discuss with Arun on this.

Thanks

0 Aravind Batni over 4 years ago in reply to Aravind Batni

TI__Expert 8885 points

Hi Bruno,

Sorry.. It is taking longer than usual. Someone will get back to you on this.

Thanks,

0 Mukul Bhatnagar over 4 years ago in reply to Aravind Batni

TI__Guru* 84005 points

Hi Bruno

We do not have much additional insight on what may be going wrong here.

One thing I wanted to check was did you or can you try internal loopback (set loopback mode to CSL_SERDES_LOOPBACK_ENABLED) and see if the results are any different?

Regards

Mukul

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66AK2H14: XFI at 1p25G