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OMAP-L138: Issues using EMDA3 to read received data

Part Number: OMAP-L138
Other Parts Discussed in Thread: OMAPL138

I’m trying to use the EDMA3 to move data received by the McASP via the AFIFO on the OMAPL-138 and am seeing some strange behavior. I’m using 4 McASP (non-contiguous) inputs and data will be received simultaneously on each input in burst mode. I want the EDMA3 to move the data out of the AFIFO after each McASP input has received 4 32-bit values. In the Read FIFO control word I have RNUMDMA set to 4 and RNUMEVT set to 16.

On the EDMA3 side, I have the PaRAM set configured as follows:

  • OPT = 0x0010004 (AB-sync)
  • SRC = 0x01D0200 (McASP AFIFO address)
  • A_B_CNT = 0x0010004 (A = 4, B = 16)
  • DST = 0x11819930 (destination buffer address)
  • SRC_DST_BIDX = 0x00040000 (DST BIDX = 4, SRC BIDX = 0)
  • LINK_BCNTRLD = 0x0000FFFF (Link = 0xFFFF)
  • SRC_DST_CIDX = 0x00000000 (SRC/DEST CIDX = 0)
  • CCNT = 0x00000001 (CCNT = 1)

With this configuration, when the DMA transfer executes it appears that 20 32-bit values get written to the destination buffer (not the 16 specified by the B value) and most of the values are incorrect. They are the last value read from the AFIFO, which I’m assuming means many more than 16 reads from the AFIFO are being executed.

After much experimenting, I’ve found that setting A to 1 and B to 15 will result in 16 32-bit values being moved from the AFIFO to the destination buffer. I’m struggling to understand why this is. Specifically, I’m wondering:

If A is the size of the data in bytes, why does the value 1 work here, and how does the EDMA know the data is actually 32 bits?

Why does B need to be 15 to move 16 values?

 Any explanations or insights about what might be going on would be greatly appreciated!

Dave Hauge

  • David,

    Please refer to the Figure 18-6 in the technical reference manual and check to see if the AB transfer has been setup correctly. You can also refer to the EDMA param setup in the MCASP LLD driver that we have provided for the configuration of this transfer for multiple channel data. The MCASP DMA configguration is provided in the file mcasp_dma.c in the folder: pdk_omapl138_1_x_xx\packages\ti\drv\mcasp\src\dma\V0

    Regards,

    Rahul

  • Thanks for the reply, Rahul. I believe I managed to get to the root cause of my issue. In the tech ref manual (I'm using SPRUH77C), Section 18.4.1.1 defines the OPT parameter and it shows that there are ten reserved bits, nine of which are read-only and all ten are zeroes after a reset. In my code, I defined a bitfield structure for the OPT parameter and only modified the non-reserved fields, which should have left the reserved fields alone. To fix my problem, I now write all zeroes to the OPT parameter first and then update the non-reserved fields. It appears that despite what the documentation says, the read-only reserved fields are not really read-only and need to be cleared to zero to have the DMA work correctly.