Schematics for eZdsp stick C5505 Rev D?

Hi Arvid,

The STEREO IN jack on the C5505 eZdsp Rev D has the MIC BIAS tied through a 1k resistor to the left channel and a 1k resistor to GND on the right channel. This enables microphones as input sources.

Make sure that the codec's MIC BIAS is disabled (AIC3204: Page 1 / Register 51: MICBIAS Configuration Register = 0x00)

You could remove resistors R26 and R34 on the back side to revert the codec back to Rev C.

I have attached the schematic here:

2117.Schematic_usbstk5505_RevD.pdf

What color is your PCB? Can you describe the effects of the discrepancy?

Thanks,
Mark

Thanks! I'll have to take a look at that.

What I am doing as a test is all ADC, DAC and analog gains set to 0 dB and the DSP simply passing buffers from the ADC to the DAC with no processing or modification.

Yeah - the discrepancy is that with the same code (mic bias is not turned on) I can feed in ~10 dB less signal to the Rev D before distortion happens somewhere in the signal chain than I can with the Rev C. This means that the noise floor is ~10dB higher for the Rev D when the output is corrected for the fact that since I can put less analog signal in, therefore I have to amplify the output more with a mixer to get the same signal level on speakers.

(edited - i made a mistake before)

ignore what i said about the 20dB difference - that was a misinterpretation of my test results. but i edited the previous post to be accurate.

Hi Arvid,

I'm a little surprised that you received the Rev. D board already, before the Spectrum Digital website is available.

The DSP on the rev D board is also changed - the rev D board (which should be colored red), has the C5505A DSP, while the previous revs A to C had the VC5505 DSP.

The C5505A DSP is code compatible with the C5515 DSP, but not 100% compatible with the VC5505. The most significant implication for the eZdsp is the PLL configuration, and I suspect this may be your problem. The C5505A/C5515 now supports system clock frequencies up to 120 MHz instead of 100 MHz (VC5505 max).

To run the C5505A/C5515 at the same frequency as the VC5505 DSP, you must program slightly different values into the Clock Generator Control Register Registers (CGCR1 - 4).

For example, these are the PLL register values to program each device to 100 MHz:

A detailed list of changes, including PLL config values for each processor, is available in the VC5505 to C5505A/C5515 Migration Guide Wiki Page, where you will find the document titled TMS320VC5504/05 to TMS320C5504/05/14/15 Application Migration Guide

Please let me know how changing the PLL affects your noise...

Hope this helps,
Mark

yes my new board is red, and has a 5505A on it.

changing the PLL, while I'm sure its the right thing to do, did not help the noise issue. I'll look into other differences.

But its actually not really a noise issue - more of an input range issue - the absolute self noise of the two Revs is close - within ~2-4 dB. The problem is that analog input to the rev D board distorts ~10dB sooner than it does with the Rev C. It seems quite possible to me that this has to do with the mic biasing setup change. I'll take a look at those schematics and continue investigating. The distortion does have an analog sound to it rather than digital.

thanks again for your help.

Hi Arvid and Mark,

this kit (Rev. D) came with a demo software like FFT Filter?

I'm validating a custom board with a C5505 and It would be very helpful.

Also, is it possible to buy this Rev.D kit?

Regards,

Alex

Alex,

You can buy the Rev D kit through the TI website. You can find the demo tests it comes with at the Spectrum Digital site:

http://support.spectrumdigital.com/boards/usbstk5505/revd/