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AM5729: PRU interrupt functionality & design reasons

Fisher Grubb
Intellectual 380 points
Part Number: AM5729
Other Parts Discussed in Thread: DRA829,

Hi all,

I almost couldn't post this question.  Each time I tried to ask this, the page just said either I needed a university or company email address, even after I changed my account over to my university email address.

Hopefully this won't stop me asking further questions.

I'm doing a research project on the BeagleBone AI PRUs, and now currently looking into their interrupts.

After looking for roughly a week, I finally realised that the PRUs don't have "real" interrupts, in the sense that the program counter doesn't jump the code to the ISR like all other processors would.

Instead, you have to manually poll register bit flags, which can be CPU cycle consuming and to me seems bad programming practise.  I didn't see this mentioned in the TRM, but actually a separate "getting started" document.

Please could someone confirm that this is true (of not having real hardware interrupts which jump to dedicated ISR functions), and also why the PRU was designed like this.

Thanks,

Fisher

  • 0
    Intellectual 380 points

    Hi all,

    Besides the above question regarding PRU interrupts, I have a similar question of the PRU design.

    I have the impression that TI wanted to pack most different CPU designs into this chip, such as:

    ARM Cortex A (dual core A15), M (dual core M4), and something realtime which was the TI designed PRU, instead of something from the Cortex R series.

    What CPU architecture or model can I compare the PRU to, and what are the main differences between this and the Cortex R series?

    Thanks,

    Fisher

  • 0 in reply to Fisher Grubb
    TI__Mastermind 37435 points

    Hi Fisher,

    You are right, the PRU's on AM57x don't have an interrupt in the real sense, as there is no pre-emption and no block of code to jump to.

    This is for historical reasons as PRU's were never intended to run complex programs. Most of the use case revolved around running very tight predictable control loops. With rare exceptions, you can tell on paper how many cycles a block of code will consume in the HW.

    As such, they have a non-pipelined and non-cached architecture.

    Having said that, the newer version of ICSS which is available in DRA829 and AM65 series of devices does support interrupts. There is support for upto 3 levels of nesting with pre-emption for fixed set of events. You can see more on this in the TRM for these devices.

    PRU's are based on a RISC architecture but it's not based on Cortex-R. It's an even simpler architecture.

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 380 points

    Hi Vineet,

    Thanks for your answer, besides the TRM and a couple of getting started documents on most of the Sitara device pages, how can I get further details on the PRU design & description?

    I'd like to understand it better, and also compare it to the Cortex R family.

    If one needs preemptive interrupts separate from Linux on the BeagleBone AI (AM5729), is the Cortex M4 the only other option?

    Thanks,

    Fisher

  • 0 in reply to Fisher Grubb
    TI__Mastermind 37435 points

    Hi Fisher,

    The PRU-ICSS wiki had all the relevant links but it's being migrated to TI.com.

    Until migration, you can access it here

    For AM57 devices, yes, Cortex M is better for pre-emptive real time tasks.

    Regards

    Vineet