I have configured the McBsp1 to receive data from the ADS1278 24 bit ADC.
The ADC clocks the first part of the data out on the first rising SCLK after FS goes high.
The McBsp expects the first data part on the first rising SCLK after FS goes low.
The ADC has no option for changing this. Can I change the McBsp to clock in data on the rising adge of FSR?
My settings are:
// Data setup for the Tx/Rx sections
pAdcForceIf->mcbspChanConfig.phaseNum = Mcbsp_Phase_SINGLE;
pAdcForceIf->mcbspChanConfig.wrdLen1 = Mcbsp_WordLength_8;
pAdcForceIf->mcbspChanConfig.wrdLen2 = Mcbsp_WordLength_8; /* Dont care for single phase */
pAdcForceIf->mcbspChanConfig.frmLen1 = 64;
pAdcForceIf->mcbspChanConfig.frmLen2 = 64; /* Dont care for single phase */
pAdcForceIf->mcbspChanConfig.frmSyncIgn = Mcbsp_FrmSync_DETECT;
pAdcForceIf->mcbspChanConfig.dataDelay = Mcbsp_DataDelay_2_BIT;
pAdcForceIf->mcbspChanConfig.compandSel = Mcbsp_Compand_OFF_MSB_FIRST;
pAdcForceIf->mcbspChanConfig.bitReversal = Mcbsp_BitReversal_DISABLE;
pAdcForceIf->mcbspChanConfig.intMode = Mcbsp_IntMode_ON_SYNCERR;
pAdcForceIf->mcbspChanConfig.rjust = Mcbsp_RxJust_RSE;//Mcbsp_RxJust_RxJUST_LZF;//Mcbsp_RxJust_RZF;
pAdcForceIf->mcbspChanConfig.dxState = Mcbsp_DxEna_ON;
// Multi channel setup
pAdcForceIf->mcbspMultiChanCtrl.multiChanMode = Mcbsp_McmMode_ALL_CHAN_ENABLED_UNMASKED;
pAdcForceIf->mcbspMultiChanCtrl.partitionSelA = Mcbsp_PartitionMode_CHAN_0_15;
pAdcForceIf->mcbspMultiChanCtrl.partitionSelB = Mcbsp_PartitionMode_CHAN_16_31;
pAdcForceIf->mcbspMultiChanCtrl.partitionMode = Mcbsp_PartitionMode_2;
// Clock setup for the Rx/Tx section
pAdcForceIf->mcbspClkConfig.frmSyncMode = Mcbsp_FsClkMode_INTERNAL; // Mcbsp_FsClkMode_EXTERNAL
pAdcForceIf->mcbspClkConfig.samplingRate = 10000;
pAdcForceIf->mcbspClkConfig.clkMode = Mcbsp_TxRxClkMode_INTERNAL; // Mcbsp_TxRxClkMode_EXTERNAL
pAdcForceIf->mcbspClkConfig.frmSyncPolarity = Mcbsp_FsPol_ACTIVE_HIGH;
pAdcForceIf->mcbspClkConfig.clkPolarity = Mcbsp_ClkPol_RISING_EDGE;
// Channel setup
// defines in soc_OMAPL1388.h
pAdcForceIf->mcbspChanparam.wordWidth = Mcbsp_WordLength_8;
pAdcForceIf->mcbspChanparam.userLoopJobBuffer = NULL;
pAdcForceIf->mcbspChanparam.userLoopJobLength = 0;
pAdcForceIf->mcbspChanparam.gblCbk = mcbsp1Error_Cb; //NULL;
pAdcForceIf->mcbspChanparam.edmaHandle = hEdma[0]; //See sprs586b table 6-14
pAdcForceIf->mcbspChanparam.edmaEventQue = CSL_EDMA3_QUE_1;// RX=1, TX=0
pAdcForceIf->mcbspChanparam.hwiNumber = CSL_EDMA3_CHA_MCBSP1_RX;//EDMA event nr See sprs586b table 6-14
pAdcForceIf->mcbspChanparam.dataFormat = Mcbsp_BufferFormat_MULTISLOT_NON_INTERLEAVED; //Mcbsp_BufferFormat_1SLOT; RO
pAdcForceIf->mcbspChanparam.enableHwFifo = TRUE;
pAdcForceIf->mcbspChanparam.chanConfig = &pAdcForceIf->mcbspChanConfig;
pAdcForceIf->mcbspChanparam.clkSetup = &pAdcForceIf->mcbspClkConfig;
pAdcForceIf->mcbspChanparam.multiChanCtrl = &pAdcForceIf->mcbspMultiChanCtrl;
pAdcForceIf->mcbspChanparam.chanEnableMask[0] = 0;
pAdcForceIf->mcbspChanparam.chanEnableMask[1] = 0;
pAdcForceIf->mcbspChanparam.chanEnableMask[2] = 0;
pAdcForceIf->mcbspChanparam.chanEnableMask[3] = 0;
// From the user-device create a DIO adapter
pAdcForceIf->dioParams.name = "/McBsp1";
pAdcForceIf->dioParams.chanParams = &pAdcForceIf->mcbspChanparam;
// DIO attributes
pAdcForceIf->dioAttrs.devid = NULL;
pAdcForceIf->dioAttrs.params = &pAdcForceIf->dioParams;
pAdcForceIf->dioAttrs.type = DEV_SIOTYPE;
pAdcForceIf->dioAttrs.devp = NULL;
// Create DIO adapter
if (DEV_createDevice("/DioMB1", &DIO_tskDynamicFxns, (Fxn)DIO_init, &pAdcForceIf->dioAttrs) != SYS_OK) {
SYS_abort("Unable to create McBsp1 DIO adapter");
return -1;
}
// SIO attributes
pAdcForceIf->SioCallback.fxn = (Fxn) SIO_ForceCallbackFunc_Cb;
pAdcForceIf->SioCallback.arg0 = 0x1234;
pAdcForceIf->SioCallback.arg1 = 0x5678;
pAdcForceIf->sioAttrs = SIO_ATTRS;
pAdcForceIf->sioAttrs.nbufs = ADC_NUM_BUFS;
pAdcForceIf->sioAttrs.align = BUFALIGN; //not 128 ???
pAdcForceIf->sioAttrs.model = SIO_ISSUERECLAIM;
pAdcForceIf->sioAttrs.timeout = SYS_FOREVER;
pAdcForceIf->sioAttrs.callback = &pAdcForceIf->SioCallback;
// Create the Rx stream
pAdcForceIf->mcbspInHandle = SIO_create("/DioMB1", SIO_INPUT, ADCFORCE_TOT_NUM_BYTES, &pAdcForceIf->sioAttrs);
if (pAdcForceIf->mcbspInHandle == NULL) {
SYS_abort("Unable to create McBsp1 Rx stream");
return -2;
}
sysCfgRegs = (CSL_SyscfgRegsOvly)CSL_SYSCFG_0_REGS;
sysCfgRegs->PINMUX1 &= ~(CSL_SYSCFG_PINMUX1_PINMUX1_7_4_MASK | /* CLKR1 */
CSL_SYSCFG_PINMUX1_PINMUX1_11_8_MASK |
CSL_SYSCFG_PINMUX1_PINMUX1_15_12_MASK | /* FSR1 */
CSL_SYSCFG_PINMUX1_PINMUX1_19_16_MASK |
CSL_SYSCFG_PINMUX1_PINMUX1_23_20_MASK | /* DR1 */
CSL_SYSCFG_PINMUX1_PINMUX1_27_24_MASK | /* DX1 */
CSL_SYSCFG_PINMUX1_PINMUX1_31_28_MASK);
sysCfgRegs->PINMUX1 = 0x02222220;//0x02202020;// see pinmuxtool
// Use Mcbsp internal clock
pAdcForceIf->mcbspSrgParams.srgInputClkMode = Mcbsp_SrgClk_CLKCPU;
// 1 bit width framesync
pAdcForceIf->mcbspSrgParams.srgFrmPulseWidth = FRAME_SYNC_WIDTH - 1; //=> 1 us
// Internal clock frequncy (SYSCLK2)
pAdcForceIf->mcbspSrgParams.srgrInputFreq = 150000000;// with CPU on 300 MHz:CSL_SYSCLK_2_FREQ = 150000000 Hz;
// McBsp parameter:
pAdcForceIf->mcbspParams = Mcbsp_PARAMS;
pAdcForceIf->mcbspParams.mode = Mcbsp_DevMode_McBSP;
pAdcForceIf->mcbspParams.opMode = Mcbsp_OpMode_DMAINTERRUPT;
pAdcForceIf->mcbspParams.enablecache = FALSE;
pAdcForceIf->mcbspParams.emulationMode = Mcbsp_EmuMode_FREE;
pAdcForceIf->mcbspParams.dlbMode = Mcbsp_Loopback_DISABLE;
pAdcForceIf->mcbspParams.clkStpMode = Mcbsp_ClkStpMode_DISABLED;
pAdcForceIf->mcbspParams.srgSetup = &pAdcForceIf->mcbspSrgParams;
pAdcForceIf->mcbspParams.pscPwrmEnable = TRUE;
//pAdcForceIf->mcbspDevAttrs = &mcbspDevAttrs;
// Device parameters and type:
pAdcForceIf->mcbspDevAttrs.devid = 1; //McBSP1
pAdcForceIf->mcbspDevAttrs.params = &pAdcForceIf->mcbspParams;
pAdcForceIf->mcbspDevAttrs.type = DEV_IOMTYPE;
pAdcForceIf->mcbspDevAttrs.devp = NULL;
// Create device for mcbsp
if (DEV_createDevice("/McBsp1", &Mcbsp_IOMFXNS, (Fxn)mcbsp1UserInit, &pAdcForceIf->mcbspDevAttrs) != SYS_OK) {
SYS_abort("Unable to create McBsp1 device");
}
