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66AK2G12: Application questions (Bootmode / QSPI setting)

Kazuki Itoh
Genius 11430 points

Part Number: 66AK2G12

Hello team,

Could you please help me to address 66AK2G12 customer questions below?

  1. bootmode pin in my system is shared with GPMC address pin.
    The GPMC is connected to FPGA and it performs 16-bit non-multiplexed memory access.
    Bootmode H/L level setting is done by PU/PD resistors.
    Could you please let me know the proper resistance value to make sure good GPMC I/F performance?
  2. About QSPI sequence setting, I want to send only OPCODE with single lane, and ADDRESS and DATA with four lanes.
    However, it doesn't work.
    Could you please let me know how to correct the register setting?
    Please find internal link here for the detail and waveforms.

Regards,

Itoh

  • 0
    TI__Guru** 116840 points

    I will let my HW colleague comment on the PU/PD resistance to ensure GPMC performance 

    On the second question, please check section 4.3.2.6 in the Technical reference manual and indicate what is the Command pin setting in the boot mode configuration.  If the value of boot mode pins are correct, the register will be setup correctly by the boot ROM on the device. I am unable to access the waveforms shared in your post.

    Regards,

    Rahul 

  • 0 in reply to Rahul Prabhu
    TI__Mastermind 22945 points

    Hi Rahul,

    Please note that customer does not use QSPI boot for the question#2.
    The QSPI access is made based on customer’s program.
    I will send you the file in separate message. You can find their register setting in the file.

    Please let me know if you need more information.

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru** 116840 points

    Tashiro-san,

    You can send me the waveforms over email for analysis however, if the customer is not using TI driver for development, we may be able to offer limited insight/support as we don`t have the source code and can`t offer support for custom QSPI driver development. Register setting will only help from QSPI IP perspective, it does not help from QSPI flash protocol implementation perspective.

    Is the QSPI operation working in any other mode like four pin or two pin mode. How was the HW validated. Has the customer tried to run the same software on a known good HW like TI evaluation platform. 

    Regards,

    Rahul