CC5505 eZDSP : Debug VS Stand Alone

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Thank for you response,

My code :

    SYS_EBSR = (SYS_EBSR & 0x80c0) | 0x1a3f;

    CONFIG_MSW = 0x0;

    PLL_CNTL2 = 0x8000;

    PLL_CNTL4 = 0x0000;

    PLL_CNTL3 = 0x0806;

    PLL_CNTL1 = 0x82FA;

    while ((PLL_CNTL3 & 0x0008) == 0)

        ;

    // Switch to PLL clk

    CONFIG_MSW = 0x1;

    // clock gating

    // enable all clocks

    IDLE_PCGCR = 0x0;

    IDLE_PCGCR_MSW = 0xFF84;

    // reset peripherals

    PER_RSTCOUNT = 0x02;

    PER_RESET = 0x00fb;

    CGR_CCSSR = 0x000b;

    for (i=0; i< 0xEFFF; i++)

        ;

    GPIO_IODIR1 = (GPIO_IODIR1 | GPIO8);

while(1)

    {

         GPIO_IODATAOUT1 = (GPIO_IODATAOUT1 | GPIO8);

        //Only to see the speed about a multiplication float

        temp += CoeffFiltre5120[j] * CoeffFiltre5120[j];

        temp += CoeffFiltre5120[j] * CoeffFiltre5120[j];

        temp += CoeffFiltre5120[j] * CoeffFiltre5120[j];

        temp += CoeffFiltre5120[j] * CoeffFiltre5120[j];

        temp += CoeffFiltre5120[j] * CoeffFiltre5120[j];

        GPIO_IODATAOUT1 = (GPIO_IODATAOUT1 & ~GPIO8);

        if(temp>0)

            data[0] = (Uint16) temp;

        else

            data[0]=0;}

When I debug the card actually I have “Configuring PLL (100.00 MHz). PLL Init Done. »

In debug mode  : GPIO8 = 93KHz and I have SYCLK on CLKOUT

In standalone mode, after several tries I haven’t SYCLK on CLKOUT and GPIO8 = 93KHz    the most case , sometimes GPIO8 = 48 KHz and on time 200KHz.

 Gauderic

Hi, to make a standalone  I tried PLL cut and paste from gel file which didnt work as the registers were not getting set.

*( short *)PCGCR1 = 0x0000;      does nothing ?

*(ioport short *)PCGCR1 = 0x0000;    appears to work for all pll reg's

I found it in an obscure 5505 migration document, hd_mig_5505_5515

are these useful bits documented elsewhere?

1st steps,

CCSv4.1.3

Gauderic,

Has this been resolve?

From you information, you have "When I debug the card actually I have “Configuring PLL (100.00 MHz). PLL Init Done. »" By looking at your cut and pasted code, you do not have any display statemment in your code. I suspect you got the display from the GEL file. This is what you typically get from GEL display statement:
Target Connection Complete.
Configure PLL (100.00 MHz).
Wait until TESTLOCKMON is high...
After checking TESTLOCKMON bit...
PLL Init Done (100.00 MHz).

Second,

    PLL_CNTL1 = 0x82FA;

works for VC5505, are you using VC5505? For C5515, it is PLL_CNTL1 = 0x8E4A;.

Third,

As Rob pointed out, you need to have the PLL registers defined:

#define PLL_CNTL1        *(ioport volatile unsigned *)0x1C20    // PLL Control Register #1

Regards.

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Steve,

I work with the CC5505 eZDSP, so with the TMX320VC5505.

I just put my final code and I have difference between “debug mode” and “standalone mode”.

I’m sure the DSP work at 100 MHz (about calculation time) on standalone mode

With : CGR_CCSSR = 0x000b;  I have SYCLK on CLKOUT on debug mode but SYCLK =0 in standalone

My code realizes:

                ADC 16 bits acquisition (with timer and 16 GPIO) and filtering on the fly

                Filtering and decimation

                FFT 2048 points (with FFT hardware)

                Display on PC with UART : Signal and FFT

On debug mode everything works

On standalone mode: Acquisition, filtering and decimation works but not FFT

Actually I'm trying to know if the problem comes from

If my variables (data_even_buf : > DARAM2_3,  data_odd_buf : > DARAM2_3, scratch_even_buf : > DARAM2_3, scratch_odd_buf : > DARAM2_3, twiddle_buf : > DARAM2_3)  for FFT, in lnkx.cmd are taken into account

If _hwafft_1024pts = 0x00ff80c2; is taken into account

Best regards

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Hello,

After several tries, my code works in standalone mode.

Effectively GEL execute different initializations (PLL 100MHZ, Peripheral_Reset, …) . I have copy and paste the GEL code.

For the FFT Hardware I need to add:

    *((volatile ioport unsigned *)(0x0001)) = 0x000E;   // Enable periph clocks in idle control register

Thank you everyone for you help

Great!!