AM3352: GPIO read/write latency

Hi Miki,

Will you provide more info regarding your inquiry "an unexpected latency in copying one GPIO to another while implementing a pass-through function in u-Boot"?

Best,
-Hong

Hello,

Trying to toggle a GPIO0 pin by running a closed loop that is setting and then clearing the output GPIO0 pin we got the below waveform. It shows that it takes about 290nsec to change the pin status. 

For a processor so powerful running at 600MHz I expected a much faster GPIO switching capability, at least 4-10 times.

Please note that the processor during the toggling test is running under u-boot, with no other process running in background.

thank you.

regards,

Miki

Hi Miki,

It seems your waveform is not readable.

1. The GPIO module interface clock provided by the L4 peripheral bus is also the functional clock and is used
through the entire GPIO module. It clocks the OCP interface and the internal logic.
Note that 100Mhz is the max frequency for all GPIO banks (GPIO_0 to GPIO_3).
Refer to Table 25-3. GPIO Clock Signals of the TRM.

2. You may also take a book at GATINGRATIO field in GPIO_CTRL Register to see if it helps for your user case.

Best,
-Hong

Hi Hong,

The GATINGRATIO does not help because we are not using the  gating functionality. Therefore , the GPIO module interface clock is 100MHz. Also the debouncing functionality is not in use.

Is any way to reduce the GPIO pin toggling period from the 578 nanoseconds? 578 nanoseconds is the value measured on our PCBA.

Thank you.

Regards,

Miki

Hi Miki,
There's a previous internal note on GPIO toggle delay of 200ns measurement done on TI EVM.
I'm trying to collect more details on measurement set-up, and will get back to you.
Best,
-Hong