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Original question:

AM5706: GPIO interrupt pins

AM5706: Interrupt to ARM via PCIe from PC(Root complex)

Takayuki Miyazaki
Genius 10120 points
Part Number: AM5706

Hi team,

Customer is investigating AM5706 device and I received inquiry about Cortex-A15’sinterrupt. Customer plans to connect AM5706(End device) to PC(Root complex) via PCI-express. Customer understand that AM5706’s L3 cache(L3_MAIN?) can be used as a dual port memory by ARM/PCIe-Core. Is that correct?

Also, Is it possible to issue an interrupt to ARM via PCIe?

Can I have your Expert’s advice/comments on this, please?

(I’m sorry. I just translated customer’s inquires.)

Best regards,

Miyazaki

  • 0
    TI__Mastermind 23125 points

    Miyazaki, 

    The OCMC on L3 interconnect is accessible by both ARM and PCIe core. It is not strictly dual-port, as it is connected to the L3 directly. But customer can access the memory via ARM or PCIe without worrying about collision. Note that ARM must manage cache if the same memory is altered by PCIe. 

    Regarding to generating interrupt to the ARM via PCIe from the RC, we usually support it via TI-specific logic, but I was not able to see it in AM57. I am double checking before saying no. will confirm back. 

    regards

    Jian