• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 101 subscribers
  • Views 558 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VM: Statistics of Cache Misses

Guoxun
Intellectual 670 points
Part Number: TDA4VM

For QNX + RTOS mode,  when an application run on TDA4VM:

How to count cache misses? Are there some api in RTOS sdk and QNX ?

How can I see cache utilization? Are there some instructions to show them?

That means : if I want to get some information about cache,for example cache misses, Cache utilization, what should I do?

For A72 Core, R5F core, C71 DSP, C66 DSP,  is the api different?

There are  "8MB SRAM with ECC",  so to it.

  • 0
    TI__Guru** 105831 points

    Hi Gouxun,

    If request is for S/W implementation to measure cache, the A72 & R5 ARM PMU counters can be used to generate cache statistics for those cores.  There are on-line ARM resources available showing examples of how PMU counters can be used to measure cache.  The TI Processor SDK for RTOS, comes with sample code within CSL directory, showing how this can be accomplished on the R5 (packages/ti/csl/test/core-r5/core_r5_pmu_test.c)

    H/W debuggers can also be used for cache/system analysis

    • The built in EVM XDS110, with Code Composer Studio can be used to generate A72 cache analysis. 
    • The Lauterbach Trace32 H/W debugger comes with QNX awareness and capability to analyze cache / system performance.

    For C66x/C7x, will get back to you with recommendation.

    Regards,

    kb

  • 0 in reply to KB
    Intellectual 670 points

    Thanks, wait for your reply about C66x/C7x.

    For the sample about R5, the icache/dchche misses means all the function about application make or single function makes ? 

    Is there an User Guide about CSL of TDA4x? 

    Can the CSL get more information about cache?  

  • 0 in reply to Guoxun
    TI__Guru** 105831 points

    Hi Gouxon,

    Regarding R5/A72 cache analysis, the cache hits/misses are per core.  Test code could be written to narrow it down to application level, or function level.

    Documentation links for the TDA4VM SDKs

    Processor SDK QNX Documentation 

    Processor SDK RTOS Documentation

    CSL Documentation is part of Process SDK RTOS documents, under the PDK component:

    PDK User Guide, CSL Module

    The aforementioned PMU example code can be seen in the Processor SDK Install directory as:

    ./packages/ti/csl/test/core-r5/core_r5_pmu_test.c

    ./packages/ti/csl/arch/r5/csl_arm_r5_pmu.h

    Regards,

    kb

  • 0 in reply to KB
    Intellectual 670 points

    Hi kb, 

    About the PMU example, I get that :the API "CSL_armR5PmuReadCntr" can be used for cache analysis of R5 core, is it?

    And is there an example about A72 ?

    In the folder {RTOS_SDK}/pdk_jacinto_07_01_00_45/packages/ti/csl/arch, I found four architecture : a53, R5, C66x,c7x,

    there is a new arch named a53 without a72, is that means: CSL support a53 arch and not support a72 for current RTOS sdk?

    If possible, can you give me some help about C66x and C7x?

    Is there an user guide about C7x cache?

    Thanks,

    Guoxun

  • 0 in reply to Guoxun
    TI__Guru** 105831 points

    Hi Guoxun,

    Regarding the ARM PMU, recommend referencing the ARM Technical Reference Manual: https://developer.arm.com/documentation/100095/0001/performance-monitor-unit/events.

    A72 examples can be readily found with an online search.  For the most part the R5 PMU example code could be ported to A72.  TI does not include an of the PMU counters for A72 in the Processor SDK for QNX.

    Regarding CSL for A53/A72, as they are both ARMv8 code in certain modules the naming was not updated, PMU code should work for both A53/A72.

    There is one thread on the e2e forums that is related to C71x forums that can be referenced at  https://e2e.ti.com/support/processors/f/791/p/907425/3358747?tisearch=e2e-quicksearch&keymatch=c71x%20cache#3358747.  As per that thread c71x cache is being measured by CCS, for documentation the TI TRM is referred to.

    Regards,

    kb