AM3352: SPI MISO timing problem at 48MHz

Ilya Kogan77

Part Number: AM3352

Hello,

We are having a problem running SPIO in master mode at 48MHz. All SPI signals are configured to be compatible with ROM bootloader execution.

The MISO falling edge is too long, and causes 1 instead of 0 being clocked in for high to low transitions.

The signal is connected to a Winbond SPI flash chip, FPGA, and a connector. The board layout traces of both the clock,

and the MISO are of about the same length. Waveforms for both 24MHz and 48MHz, and for the same SPI flash command are below:

over 4 years ago

0 Nick Saulnier over 4 years ago

TI__Guru** 100800 points

Hello Ilya,

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* What software are you running on the AM3352?

Regards,

Nick

0 Ilya Kogan77 over 4 years ago in reply to Nick Saulnier

Intellectual 355 points

0 Ilya Kogan77 over 4 years ago in reply to Ilya Kogan77

Intellectual 355 points

Hello Nick,

We're using uCos-II RTOS.

Thanks,

Ilya

0 Dillon Frank over 4 years ago in reply to Ilya Kogan77

TI__Intellectual 2615 points

Hi Ilya,

And are you using the most up to date version?

Regards,

Dillon

0 Ilya Kogan77 over 4 years ago in reply to Dillon Frank

Intellectual 355 points

Hi,

I don't think it has anything to do with the RTOS. When we lifted the flash pin up disconnecting it from the MPU, FPGA, and connector the waveform became much more reasonable.

Disconnecting the other destinations one at a time will be rather difficult, and time consuming. It may or may not be the MPU though it is hard to imagine that unconfigured FPGA, and a connector pin

not connected to anything else may be a problem.

Thanks,

Ilya

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AM3352: SPI MISO timing problem at 48MHz