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AM3352: AIN4 measurement reading differently on a new batch of parts (lower than typical)

Lauren Mayfield
Expert 7895 points
Part Number: AM3352

Hi team,

My customer is seeing a potential quality issue with AM3352. I wanted to run this by you to make sure it doesn't have to do with their application before we move to an FA. Please see the below information, and once this ticket is assigned I can share the schematics internally.

I have a question regarding the default AIN4 (C8) value of AM3352BZCZA60.

Out vendor using the new batch of AM3352BZCZA60 and they notice the AIN4 value is lower than the lot they use before. The output value on previous date code(1545) value of AIN4 normally in between 190-200mVs and current date code (MPN# AM3352BZCZA60, DC 2023) they use right now the value is between 90-150mVs.

 

We are using AIN4 as a as battery VSENSE reading, and without the battery connected, I assuming the voltage should be as low as possible, but I am not sure if this is correct or not. Can you confirm with us, what is the value we should expecting to read if there is no battery present. and also can you help to check is there any update between t two different data code? 

To clarify, the old batch they have was purchased a few years ago, and the AIN4 measurement is aways above 150mv. The measurement on the new batch, the value drops below 150mv, and lowest one they see is 90mv. Both measurements are with the battery disconnected. There is no change between the code or testing method.

Thank you,

Lauren

  • 0
    TI__Guru 62855 points

    What frequency is your ADC clock? 

    The ADC clock needs to be greater than 1MHz to ensure the conversion period is short enough that the voltage applied the sampling capacitor doesn't bleed-off due to internal leakage paths before the conversion is complete. We have seen the ADC give erratic values when the ADC clock is too slow.

    Regards,
    Paul

  • 0 in reply to peaves
    TI__Expert 7895 points

    Hi Paul, it's 24 MHz

  • 0 in reply to Lauren Mayfield
    TI__Expert 7895 points

    Sorry, meant to say 2.4MHz

  • 0 in reply to Lauren Mayfield
    TI__Expert 7895 points

    Hi Paul,

    Any update on this? Their clock has been the same on older batches of chips as well and those were working properly.

  • 0 in reply to Lauren Mayfield
    TI__Guru 62855 points

    Sorry for the delayed reply. I was completely absorbed with another task that had to be completed.

    I would not expect internal leakage to be causing an offfset issue if the output of the ADC clock pre-divider is configured to produce a 2.4 MHz clock.

    Has there been any change to external circuits sourcing the ADC inputs?  Can you include a snapshot of the source circuits and connections to ADC inputs. It may also be helpful to include ADC power supply connections as well as the VREFP and VREFN sources.

    What is the source impedance of the circuits connected to the ADC inputs?

    Have you changed anything related to the ADC configuration?

    Are you operating the ADC in single-ended mode or differential mode?  If single-ended, have you configured the ADC negative input (INM) such that it is connected to VREFN?  See the snapshot included below.

    It may be helpful if you can dump the ADC registers so I can review your configuration.

    Regards,
    Paul