AM5726: DPLL_ABE Lock not being achieved.

Daksh Jaitly

Prodigy 150 points

Part Number: AM5726

Hi,

Im trying to bring up the McASP modules on the AM5726 SoC.

Clock Config :

SYS_CLK1 - supplies 27M

All muxes for DPLL_ABE are set to pass SYS_CLK1 as reference and bypass clock.

the lock sequence is followed from TRM (gel version provided in CCS also tried). the DPLL_CORE and DPLL_PER have locked successfully. the DPLL_ABE always stays in "transient state" and is never able to get a lock.

the McASP modules are programmed to get clocks from the DPLL_ABE - Divided version of PER_ABE_X1_GFCLK.

Any suggestions would be much appreciated.

Thanks,

Daksh

over 5 years ago

0 Karan Saxena over 5 years ago

TI__Guru* 78165 points

Hi Daksh,

Which SDK are you running here?

Regards,

Karan

0 Daksh Jaitly over 5 years ago in reply to Karan Saxena

Prodigy 150 points

Hi Karan,

the SDK is RTOS (6.03.00.106).

the issue seems to be in timing. I had to add a couple of dummy statements to delay the locking process. the way I did was just simply reading back the registers and waiting on a while loop until the value latches. the PLL can now lock.

is this known?

Thanks,

Daksh

0 Stanley Liu over 5 years ago in reply to Daksh Jaitly

TI__Guru 50045 points

Yes, we typically wait in a while loop until the status is locked.

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AM5726: DPLL_ABE Lock not being achieved.