J721EXSOMXEVM: J721e: SerDes DTS change for custom board

Satish Lal Das2

Expert 1900 points

Part Number: J721EXSOMXEVM

Hello,

We have our custom board and the SerDes ports are mapped as below -

PORT 0 - SGMII1 and SGMII2

PORT 1 - SGMII3 and SGMII4

PORT 2 - PCIE0

PORT 3 - PCIE1

PORT 4 - SGMII5, SGMII6, SGMII7, SGMII8

Could you please let me know what Changes I have to make for following nodes?

&serdes_ln_ctrl {
	idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
		      <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
		      <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
		      <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
		      <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
};

&serdes_wiz3 {
	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
};

Also Could you please let me know where I can find the macro (#define) for SGMII. For example in following node I can find "PHY_TYPE_PCIE" in "/include/dt-bindings/phy/phy.h" but I did not find anything related to SGMII.

&serdes2 {
	serdes2_pcie_link: link@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
	};
};

Thank you,

Satish

over 4 years ago

0 Vineet Roy over 4 years ago

TI__Mastermind 37435 points

Hi Satish,

I will check with the Ethernet and Linux team and get back to you

Regards

Vineet

0 Vineet Roy over 4 years ago in reply to Vineet Roy

TI__Mastermind 37435 points

Hi Satish,

Configuring Ethernet is fully handled by the ethernet firmware.

"Also Could you please let me know where I can find the macro (#define) for SGMII. For example in following node I can find "PHY_TYPE_PCIE" in "/include/dt-bindings/phy/phy.h" but I did not find anything related to SGMII."

The SERDES driver for J7ES in Linux supports only PCIe and USB3. SGMII configurations are done by Ethfw. Though the latest kernel adds macro PHY_TYPE_SGMII, the SERDES driver does not have support for SGMII.

For the serdes_ln_ctrl, you have to use macros from include/dt-bindings/mux/mux-j721e-wiz.h based on their usecase.

PORT 2 - PCIE0

PORT 3 - PCIE1

SERDES2 cannot be connected to PCIe instance 0. It can be connected only to PCIe instance 2.

Similarly SERDES3 cannot be connected to PCIe instance PCIe instance 1. t can be connected only to PCIe instance 3. If the PCIe instance number is understood, the serdes_ln_ctrl should be added like below.

&serdes_ln_ctrl {

idle-states = <SERDES0_LANE0_QSGMII_LANE1>, <SERDES0_LANE1_QSGMII_LANE2>,

<SERDES1_LANE0_QSGMII_LANE3>, <SERDES1_LANE1_QSGMII_LANE4>,

<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,

<SERDES3_LANE0_PCIE3_LANE0>, <SERDES3_LANE1_PCIE3_LANE1>,

<SERDES4_LANE0_QSGMII_LANE5>, <SERDES4_LANE1_QSGMII_LANE6>, <SERDES4_LANE2_QSGMII_LANE7>, <SERDES4_LANE3_QSGMII_LANE8>;

};

I am still trying to get some more answers from Ethernet team regarding EthFW.

Regards

Vineet

0 Satish Lal Das2 over 4 years ago in reply to Vineet Roy

Expert 1900 points

Hi Vineet,

Thank you for pointing on the SERDES port mapping. I double-checked with our hardware team and turned out that our hardware is set up correctly just the schematic needs correction. In our, HW SerDes2 is mapped to PCIe2, and SerDes3 is mapped to PCIe3.

I do have a follow-up question on this -

"The SERDES driver for J7ES in Linux supports only PCIe and USB3. SGMII configurations are done by Ethfw. Though the latest kernel adds macro PHY_TYPE_SGMII, the SERDES driver does not have support for SGMII."

1) Are you planning to update SerDes Driver to add SGMII support at some point in the future?

2) In SDK 7.1 I Linux kernel at "/drivers/phy/cadence/phy-cadence-torrent.c" I noticed that several PHY_TYPE_SGMII macros are used which made me think that SGMII support is available in SerDes driver in this kernel. Am I reading it wrong here?

Thank you again for your help.

Satish

0 Vineet Roy over 4 years ago in reply to Satish Lal Das2

TI__Mastermind 37435 points

Hi Satish,

Since we are following this over email, I am closing this thread.

We can re-open if required.

Regards

Vineet

0 Satish Lal Das2 over 4 years ago in reply to Vineet Roy

Expert 1900 points

Thank you Vineet.

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J721EXSOMXEVM: J721e: SerDes DTS change for custom board