TDA4VM BOOTMODE(POST) and other question

Hi Xiaowei,

In TDA4VM TRM, the BOOTMODE can be configured for performing POST, and some registers are discribed for indicating failulre detected by POST. There are 3 questions about POST as shown below.

[registers:“5.1.1.4.88 CTRL_MMR_WKUP_POST_STAT”]

1. How to handle POST failure? Whether it can only be detected by actively reading the register after system initialization, any other ways recommended for POST failure handling?

[TI] The CTRL_MMR_WKUP_POST_STAT can be read for the HW POST results after initialization.  Examples of this are present in Processor SDK RTOS 7.1 in:

ti-processor-sdk-rtos-j721e-evm-07_01_00_11/mcusw/mcuss_demos/boot_app_mcu_rtos

How any error is handled or further communicated is implementation specific.

2. What function/hardware blocks be checked during POST?   In TRM, the description is "MCU R5 PBIST&LBIST+ DMSC LBIST"; but in safety manual, the description is "make sure all logic&memory&cores..." , looks like the scope of description from safety manual is bigger than from TRM? 

[TI] PBIST and LBIST examples are included in Processor SDK 7.1.  Code can be referenced for usage.

As part of SBL boot flow reference:

                ti-processor-sdk-rtos-j721e-evm-07_01_00_11/mcusw/mcuss_demos/boot_app_mcu_rtos

         In the SDK RTOS 7.1 examples can be found at:

• • •  ti-processor-sdk-rtos-j721e-evm-07_01_00_11/pdk_jacinto_07_01_00_45/

Reference CSL Apis and test code:

• • • /packages/ti/csl/src/ip/pbist/V0/
    •  /packages/ti/csl/src/ip/lbist/V0/
    • /packages/ti/csl/test/lbist/j721e
    • /packages/ti/csl/test/pbist/j721e

The diagrams providing an overview of code are available in SDK RTOS 7.1 at:

/packages/ti/csl/docs/bist_design_diagrams/ 

The cores/modules that support PBIST/LBIST can be seen in the TRM by by searching on LBIST /PBIST.

3. Can POST be used to detect latent fault(including all safety mechanism in MAIN domain and MCU domain)?

[TI] Power-On Self-Test (POST) will run structural test immediately after power-up, before

device boot and make sure that all logic, memories and processor cores involved are heathy before

running the application.

Are there any test reports for proving the effectiveness of safety mechanisms maintained in the TDA4VM safety manual? Can you provide us with relevant docs?

[TI] Please contact your local TI representative, for further information on test reports.

Regards,

kb