AM5716: DDR troubleshooting - locking up after browsing memory in CCS

Jason Bender1

Part Number: AM5716

I am commissioning a new board design for the Sitara AM5716 processor and have not yet been able to get the DDR memory working.

So far I have successfully:
- Powered the system and checked all voltages, including DDR VTT
- Connect to the ARM, loaded and executed the TI supplied GEL files
- Connected to the DSP and other cores
- Ran a DSP/BIOS application on the DSP core (entirely in L2) --- this was a test only, I am not running any code at all until I can get the DDR working...
- Filled out the 'EMIF_RegisterConfig' spreadsheet to generate the EMIF parameters and LISA map configs
- Created my own GEL files (heavily leveraged from TI's starting point), changed DLL's to use 27MHz SYSCLK
- Ran the TI supplied DSS script 'am57xx-ddr.dss' to print diagnostic info, and verified the DDR PHY clock is configured for 666MHz
After running my newly created Dxo GEL scripts, the system registers can be viewed normally. However, if the memory browser is used to view any DDR memory location, the debugger loses connection to the target:

CortexA15_0: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x231: (Error -1205 @ 0x80000000) Device memory bus has an error and may be hung. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.2.1.00046) 
CortexA15_0: Trouble Reading Memory Block at 0x80000000 on Page 0 of Length 0x231: (Error -2130 @ 0x80000000) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.2.1.00046) 
CortexA15_0: JTAG Communication Error: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 9.2.1.00046)

A hard reset is needed before I can reconnect (a soft reset and/or restarting the debug session does not recover with other errors indicating that no registers can be accessed).

I've attached the 'EMIF_RegisterConfig' spreadsheet, the GEL files that I am running on target connect, as well as the output from the 'am57xx-ddr.dss' script just before the memory hang.

Perhaps you can catch something that I have missed? Any help is greatly appreciated. Any additional scripts, diagnostics, or tests I could do to narrow down the problem would certainly help.

Thank-you!
-Jason

Attachments.zip

over 4 years ago

0 Jason Bender1 over 4 years ago

Prodigy 210 points

Update to make sure I've provided all relevant information...

The DDR on this board is single Alliance #AS4C256M16D3LC-12BCN which is a 4Gb 256M x 16 bit DDR3L (organized as 32Mbit x 16 I/Os x 8 bank)
www.mouser.com/.../AllianceMemory_4G_DDR3L_AS4C256M16D3LC_March2020_R-1826861.pdf

Schematic included:
(AM5716 pins shown in red, with the DDR pins shown in black)

0 Jason Bender1 over 4 years ago

Prodigy 210 points

I was able to make some progress! When creating my own GEL scripts from the TI supplied versions, I did not include the 'AM571x_reset_emif_params_ddr3_666' function. I thought that it only reset parameters that are otherwise loaded from the 'EMIF_RegisterConfig' spreadsheet, but that is not correct.

This function sets several (obviously important) variables that properly configure various registers in the EMIF. The takeaway is that the TI spreadsheet does *not* capture the full configuration and parameters to configure the DDR properly. For the curious, I've distilled the function down to show what parameters are set only by the 'AM571x_reset_emif_params_ddr3_666' function:

Also, in case anyone ends up here, be aware that this still does not work! I can now view the DDR memory without a lockup, but the data is garbled with several read and write errors. The data errors present as some quite interesting patterns, though! I'll follow up with another post if I can't figure it out and get it fully functional...

    EMIF_PHY_DIS_CALIB_RST       = 0U;
    EMIF_PHY_DLL_LOCK_DIFF       = 0x10U;
    EMIF_PHY_FAST_DLL_LOCK       = 0U;

    EMIF_PHY_USE_RANK0_DELAYS    = 1U; 

    EMIF_PHY_GATELVL_INIT_MODE   = 0x01U;
    EMIF_PHY_FIFO_WE_IN_DELAY    = 0x00U;
    EMIF_PHY_CTRL_SLAVE_DELAY    = 0x00U;
    EMIF_PHY_RD_DQS_SLAVE_DELAY  = 0x20U;
    EMIF_PHY_WR_DQS_SLAVE_DELAY  = 0x60U;
    EMIF_PHY_WR_DATA_SLAVE_DELAY = 0x80U;

    PWR_MGMT_CTRL      = 0x00000000U;
    OCP_CONFIG         = 0x0A500000U;
    IODFT_TLGC         = HW_RD_REG32(base_addr +
                                     EMIF_IODFT_TLGC);
    DLL_CALIB_CTRL     = 0x00050000U;
    ZQ_CONFIG          = 0x5007190BU;
	
    RDWR_LVL_RMP_WIN   = HW_RD_REG32(base_addr +
                                     EMIF_READ_WRITE_LEVELING_RAMP_WINDOW);

    DDR_PHY_CTRL_2     = HW_RD_REG32(base_addr +
                                     EMIF_DDR_PHY_CONTROL_2);
    PRI_COS_MAP        = 0x00000000U;
    CONNID_COS_1_MAP   = 0x00000000U;
    CONNID_COS_2_MAP   = 0x00000000U;
    RD_WR_EXEC_THRSH   = 0x00000305U;
    COS_CONFIG         = 0x00FFFFFFU;

    // EMIF_PHY_WR_DATA_SLAVE_RATIO
    temp = 0x7FU;
    EXT_PHY_CTRL_12    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_13    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_14    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_15    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_16    = (temp << 16U) | (temp << 0U);

    // EMIF_PHY_GATELVL_INIT_RATIO
    temp = 0U;
    EXT_PHY_CTRL_26    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_27    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_28    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_29    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_30    = (temp << 16U) | (temp << 0U);

    // EMIF_PHY_WRLVL_INIT_RATIO
    temp = 0U;
    EXT_PHY_CTRL_31    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_32    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_33    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_34    = (temp << 16U) | (temp << 0U);
    EXT_PHY_CTRL_35    = (temp << 16U) | (temp << 0U);

    EXT_PHY_CTRL_36    = HW_RD_REG32(base_addr +
                                     EMIF_EXT_PHY_CONTROL_36);
    EXT_PHY_CTRL_36    = HW_RD_REG32(base_addr +
                                     EMIF_EXT_PHY_CONTROL_36_SHADOW);

    SDRAM_CONFIG_2     = 0x08000000U;

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AM5716: DDR troubleshooting - locking up after browsing memory in CCS