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Query related to McBSP, SDMA & EDMA3 LLD

Girisha SG
Intellectual 970 points
Other Parts Discussed in Thread: SYSCONFIG

For the below McBSP configuration when will SDMA receive interrupt ?

rcr2_reg      = 0x00000001
rcr1_reg      = 0x000003A0
xcr2_reg      = 0x00000001
xcr1_reg      = 0x000003A0
srgr2_reg      =  0x000010FF
srgr1_reg      =  0x00001F00
mcr2_reg      = 0x00000201
mcr1_reg      = 0x00000201
rcera_reg      =  0x0000000F
rcerb_reg      =  0x00000000
xcera_reg      =  0x0000000F
xcerb_reg      =  0x00000000
pcr_reg      = 0x00000F03
sysconfig_reg  =  0x00000000
thrsh2_reg   =  0x00000000
thrsh1_reg   =  0x00000000
irqenable_reg  =  0x00000000
xccr_reg      =  0x00001008
rccr_reg      =  0x00000808

1. Does it receive for every word i.e. for every 32 bits ?

Or

2. Does it receive after every frame ?

Or

3. Does it generate after every 1024 byte (As I am getting callback registered with EDMA3 invoked after 1024 bytes are filled)?

Note:

I am sure the McBSp configuration is correct as it is working on with EDMA3(from DSP side) and now I am porting on ARM with SDMA & observing noisy output(I am assuming ISR in SDMA is getting called after every 1024 bytes !) Please let me know is it right or wrong.

This is EXTREMELY IMPORTANT TO ME !

  • 0
    TI__Mastermind 28015 points

    The McBSP initiates a DMA request for every word received due to the THRSH1_REG = 0x0.

    Here's the register descripton from the TRM:

    Receive buffer threshold value. The DMA request (if RW 0x00

    enabled) of interrupt assertion (if enabled)is triggered if

    the number of occupied locations in the receive buffer are

    above or equal to the RTHRESHOLD value + 1. Also,

    this value (RTHRESHOLD value + 1) indicates the

    number of words transferred during a receive data DMA

    request, if receive DMA is enabled.

    As mentioned in your other thread, the THRSH1_REG +1 setting should mach the DMA frame size if configured for full frame transfers.

      Paul

  • 0 in reply to PaulM
    Intellectual 970 points

    After making the THRSH1_REG = 0xFF and necessary changes in the SDMA side I am hearing some audio. I am using SDMA channels in chain linking mode. First time bits for both the SDMA channels are set in irqstatus register and I clear them then during 2nd request bits set for only 2nd channel but 3rd time it is again set for both the channels and same pattern continues ... I would like to know why it is so ... ?

  • 0 in reply to Girisha SG
    TI__Mastermind 28015 points

    Girisha

    Let me investigate...

      Paul

     

  • 0 in reply to Girisha SG
    TI__Mastermind 28015 points

    Girisha SG said:

    After making the THRSH1_REG = 0xFF and necessary changes in the SDMA side I am hearing some audio. I am using SDMA channels in chain linking mode. First time bits for both the SDMA channels are set in irqstatus register and I clear them then during 2nd request bits set for only 2nd channel but 3rd time it is again set for both the channels and same pattern continues ... I would like to know why it is so ... ?

    Given our dialogue in other threads I suspect that the irqstatus issues is due to you printing diagnostics from the ISR and therefore missing interrupts. 

      Paul