DM3730/Beagle board XM Warm reset issue

Alain Philippe

Prodigy 60 points

Other Parts Discussed in Thread: DM3730, SYSBIOS

When the MLO is excecuting the following code:

sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */

sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */

sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */

sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */

sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */

wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);

/* Getting the base address to MPU DPLL param table */

dpll_param_p = (dpll_param *) get_mpu_dpll_param();

It gets stuck at the line in red for 5 seconds and then timeouts. It looks like the peripheral clock does not settle.

This code works fine on the Beagleboard. The clock comes up just fine on a hard reset or power-on-reset.

Has anyone experienced the same problem? What's the solution?

Alain

over 14 years ago

0 JJD over 14 years ago

TI__Guru* 86180 points

Before changing the m/n values in the PLL, it should be in bypass mode. The xloader may assume it is running from a POR and thus may assume the PLL is in bypass mode before changing its parameters. From a warm reset this may not be the case. May have to explicitly set the PLL into bypass before this code executes.

regards,

James

0 Javier Martin19423 over 14 years ago in reply to JJD

Intellectual 455 points

Hi,

I'm having the same problem with last version of x-load. The problem is inside the function "prcm_init()". The code gets stuck in the red line waiting for DPLL4 ( ST_PERIPH_CLK) to be locked, but that won't happen.

The problem occurs after a warm reset (software) and not after a POR (cold reset hardware).

Have you found the solution already?

----

/******************************************************************************
* prcm_init() - inits clocks for PRCM as defined in clocks.h
*   -- called from SRAM, or Flash (using temp SRAM stack).
*****************************************************************************/
void prcm_init(void)
{
    u32 osc_clk = 0, sys_clkin_sel;
    dpll_param *dpll_param_p;
    u32 clk_index, sil_index;

    /* Gauge the input clock speed and find out the sys_clkin_sel
    * value corresponding to the input clock.
    */
    osc_clk = get_osc_clk_speed();
    get_sys_clkin_sel(osc_clk, &sys_clkin_sel);

    sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel);    /* set input crystal speed */

    /* If the input clock is greater than 19.2M always divide/2 */
    if (sys_clkin_sel > 2) {
        sr32(PRM_CLKSRC_CTRL, 6, 2, 2);    /* input clock divider */
        clk_index = sys_clkin_sel / 2;
    } else {
        sr32(PRM_CLKSRC_CTRL, 6, 2, 1);    /* input clock divider */
        clk_index = sys_clkin_sel;
    }

    sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */

    /* The DPLL tables are defined according to sysclk value and
    * silicon revision. The clk_index value will be used to get
    * the values for that input sysclk from the DPLL param table
    * and sil_index will get the values for that SysClk for the
    * appropriate silicon rev.
    */
    sil_index = get_cpu_rev() - 1;

    /* Unlock MPU DPLL (slows things down, and needed later) */
    sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
    wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);

    /* Getting the base address of Core DPLL param table */
    dpll_param_p = (dpll_param *) get_core_dpll_param();
    /* Moving it to the right sysclk and ES rev base */
    dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
    /* CORE DPLL */
    /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
    sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
    wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);

    /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
    work. write another value and then default value. */
    sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1);     /* m3x2 */
    sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);    /* m3x2 */
    sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2);    /* Set M2 */
    sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m);    /* Set M */
    sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n);    /* Set N */
    sr32(CM_CLKSEL1_PLL, 6, 1, 0);    /* 96M Src */
    sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV);    /* ssi */
    sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV);    /* fsusb */
    sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV);    /* l4 */
    sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV);    /* l3 */
    sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV);    /* gfx */
    sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM);    /* reset mgr */
    sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel);    /* FREQSEL */
    sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK);    /* lock mode */
    wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);

    /* Getting the base address to PER DPLL param table */
    dpll_param_p = (dpll_param *) get_per_dpll_param();
    /* Moving it to the right sysclk base */
    dpll_param_p = dpll_param_p + clk_index;
    /* PER DPLL */
    sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
    wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
    sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2);    /* set M6 */
    sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2);    /* set M5 */
    sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2);    /* set M4 */
    sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2);    /* set M3 */

    if (beagle_revision() == REVISION_XM) {
            sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2);   /* set M2 */
            sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M);   /* set m */
            sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N);    /* set n */
    } else {
        sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2);    /* set M2 */
        sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m);    /* set m */
        sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n);    /* set n */
    }

    sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);    /* FREQSEL */
    sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);    /* lock mode */
    wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);

0 R1234 over 13 years ago in reply to Javier Martin19423

Intellectual 420 points

Did anyone manage to fix the watchdog issue on beagleXM boards?

Thanks.

0 R1234 over 13 years ago in reply to R1234

Intellectual 420 points

I got a reply from a TI employee, he supplied met with a patch.

The patch will detect a warm boot and reset the device again with a cold reboot.

The main reason for this problem is that the PLL4 settings are not always correct after warm boot.

==== PATCH ====

This patch fixes the warm/watchdog reset apparent hang on the Beagleboard-xM (OMAP3630/DM3730 device).

Signed-off-by: Benoit Parrot <bparror@ti.com>

---

diff -X /home/a0869644/xloaddiff -purN orig/x-load-1.5.0+r24+gitr04b1732220078d47c18a84cbafc52e45db71f13d//board/omap3530beagle/omap3530beagle.c x-load-min/board/omap3530beagle/omap3530beagle.c

--- orig/x-load-1.5.0+r24+gitr04b1732220078d47c18a84cbafc52e45db71f13d//board/omap3530beagle/omap3530beagle.c 2011-07-05 23:22:00.000000000 -0500

+++ x-load-min/board/omap3530beagle/omap3530beagle.c 2011-11-10 16:31:53.957520000 -0600

@@ -181,6 +181,36 @@ u32 get_cpu_rev(void)

}

+u32 is_cpu_family(void)

+ u32 cpuid = 0, cpu_family = 0;

+ u16 hawkeye;

+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));

+ if ((cpuid & 0xf) == 0x0) {

+ cpu_family = CPU_OMAP34XX;

+ } else {

+ cpuid = __raw_readl(OMAP34XX_CONTROL_ID);

+ hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;

+ switch (hawkeye) {

+ case HAWKEYE_OMAP34XX:

+ cpu_family = CPU_OMAP34XX;

+ break;

+ case HAWKEYE_AM35XX:

+ cpu_family = CPU_AM35XX;

+ break;

+ case HAWKEYE_OMAP36XX:

+ cpu_family = CPU_OMAP36XX;

+ break;

+ default:

+ cpu_family = CPU_OMAP34XX;

+ break;

+ }

+ return cpu_family;

/******************************************

* cpu_is_3410(void) - returns true for 3410

******************************************/

@@ -520,13 +550,21 @@ void prcm_init(void)

sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */

+ if (is_cpu_family() == CPU_OMAP36XX) {

+ /* On Warm (Watchdog,RST_GS,emulator) reset after the ROM gets executed

+ the DPLL4_CLKINP_DIV is set. It SHOULD be clear, otherwise all of the

+ peripherals will be running 6.5 times slower than they should making

+ it appear as though the reset did not take place */

+ sr32(PRM_CLKSRC_CTRL, 8, 1, 0);

+ }

/* The DPLL tables are defined according to sysclk value and

* silicon revision. The clk_index value will be used to get

* the values for that input sysclk from the DPLL param table

* and sil_index will get the values for that SysClk for the

* appropriate silicon rev.

- sil_index = get_cpu_rev() - 1;

+ sil_index = !(get_cpu_rev() == CPU_3XX_ES10);

/* Unlock MPU DPLL (slows things down, and needed later) */

sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);

diff -X /home/a0869644/xloaddiff -purN orig/x-load-1.5.0+r24+gitr04b1732220078d47c18a84cbafc52e45db71f13d//include/asm/arch-omap3/cpu.h x-load-min/include/asm/arch-omap3/cpu.h

--- orig/x-load-1.5.0+r24+gitr04b1732220078d47c18a84cbafc52e45db71f13d//include/asm/arch-omap3/cpu.h 2011-05-23 06:53:15.000000000 -0500

+++ x-load-min/include/asm/arch-omap3/cpu.h 2011-11-10 14:42:38.097873000 -0600

@@ -38,6 +38,9 @@

#define TAP_IDCODE_REG (OMAP34XX_TAP_BASE+0x204)

#define PRODUCTION_ID (OMAP34XX_TAP_BASE+0x208)

+/* OMAP 34XX/35XX/36xx/37xx Control ID */

+#define OMAP34XX_CONTROL_ID (OMAP34XX_WAKEUP_L4_IO_BASE + 0xa204)

/* device type */

#define DEVICE_MASK (BIT8|BIT9|BIT10)

#define TST_DEVICE 0x0

@@ -182,6 +185,7 @@

#define CM_FCLKEN1_CORE 0x48004a00

#define CM_ICLKEN1_CORE 0x48004a10

#define CM_ICLKEN2_CORE 0x48004a14

+#define CM_IDLEST1_CORE 0x48004A20

#define CM_CLKSEL_CORE 0x48004a40

#define CM_FCLKEN_GFX 0x48004b00

#define CM_ICLKEN_GFX 0x48004b10

@@ -209,7 +213,8 @@

#define PRM_CLKSEL 0x48306d40

#define PRM_RSTCTRL 0x48307250

#define PRM_CLKSRC_CTRL 0x48307270

+#define PRM_RSTTST 0x48307258

#define SYSCLKDIV_2 (0x1 << 7)

/* SMX-APE */

0 ram over 12 years ago in reply to R1234

Intellectual 640 points

I am experiencing lots of Error when booting BeagleBoard_XM (CortexA8) with SYSbios through JTAG XDS100v2 from CCSv5.3.

And the errors seems coming from GEL file and even after searching and posting in various TI-e2e2 forum i didn't find any solution for this.

Every-time i am trying to flash my SYSbios application, it seems the GEL is resetting the Target and making the board unresponsive and sometimes it end up with exception.

Any one can come forward and give a notice to my problem....

Thanks in Advance

0 Haihong Luo1 over 11 years ago in reply to R1234

Prodigy 20 points

R1234 wrote the following post at Nov 11 2011 05:32 AM:

I got a reply from a TI employee, he supplied met with a patch.

...

Hi, pal,

Can I have the patch file you received from TI?

Seems that the code you pasted has some macros added to cpu.h, but not "mentioned" in .c patch.

Or can any helpful TI employee has a download link, to x-loader version/variant that already has this patch built-in and tested, be it ver 1.47, 1.5.1 or 1.51?

0 Haihong Luo1 over 10 years ago in reply to R1234

Prodigy 20 points

Hi, Dear R1234 & Brad Griffis,

I met exactly the same issue from same series of CPU, DM37xx, using x-loader 1.47; and the support for this watchdog issue on my pilot project to further sell more TI chips are getting quite nasty.

Could you guys, please, send me both the patch file and the x-loader v1.50 variant it's patched against? (patched x-loader is also welcome? Or any TI offical web link to download one?)

My email is luohaihong@gmail.com. Many thanks in advance

R1234 said:

I got a reply from a TI employee, he supplied met with a patch.

The patch will detect a warm boot and reset the device again with a cold reboot.

The main reason for this problem is that the PLL4 settings are not always correct after warm boot.

==== PATCH ====

This patch fixes the warm/watchdog reset apparent hang on the Beagleboard-xM (OMAP3630/DM3730 device).

......

Processors

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DM3730/Beagle board XM Warm reset issue