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66AK2G12: reference clock for PCIe of Rootcomplex and Endpoint

user3788809
Intellectual 900 points
Part Number: 66AK2G12

Hi,

Our design is supposeed to use 66AK as not only rootcomplex but also endpoint of PCIe.

According to the 66AK2Gx Schematic Checklist, it says "If the PCIE subsystem is connected as an endpoint, it is always best to connect the reference clock
provided by the root complex. If the root complex provides a spread-spectrum reference clock, the
PCIE subsystem may not connect if a separate clock is connected to the PCIE_CLK."

This means " the common Clock architecture" is recommended.

On the other hand, generally speaking, te Separate Clock architecture for 5.0 Gb/S(Gen 2) is also covered.

As for 66Ak, If 5.0 Gb/S(Gen 2) is selected, is it possible to adopt the Separate Clock architecture?

【the Separate Clock architecture】

66AK_1   ------(PCIe)----->   66AK_2

     ↑                                                 ↑

refclk_1                            refclk_2   

【 the common Clock architecture】

66AK_1   ------(PCIe)----->   66AK_2

     ↑                                              　 ↑

refclk_1 ---------------------------↑

Thanks.

  • 0
    TI__Mastermind 27890 points

    Hello,

    You are correct: use of the PCIe Common Clock Architecture is recommended as outlined in the device TRM. Use of the PCIe Separate Reference clocking architecture is not recommended for this device.

  • 0 in reply to -DK-
    Intellectual 900 points

    Hello,

    Thank you for your response.

    Why is not the use of the PCIe Separate Reference clocking architecture recommended?

    In terms of "whether it is possible to use the PCIe Separate Reference clocking architecture or not", how about this?

    ( though I understood the PCIe Separate Reference clocking architecture is not recommended)

    (I changed quastion)

    Can 66AK select the "Common Clock Architecture"? (Method to recover the clock from received data on the receiving side)

    (I changed quastion again, January 28th)

    Can 66AK select the "Data Clock Architecture"? (Method to recover the clock from received data on the receiving side)

    Please see below:Figure 3. Data Clock Architecture

    If possible, which PCIE configuration resister should be set?

    Thanks.

  • 0 in reply to -DK-
    Intellectual 900 points

    I missed expresstion.

    I would like to know whether 66AK can select the "Data Clock Architecture (Method to recover the clock from received data on the receiving side)" or not.

    Please see below:Figure 3. Data Clock Architecture

    I could not find the PLL to recover the clock from received data on the receiving side in TRM and data manual.

    【 the Data Clock Architecture】

    66AK_1   ------(PCIe gen 2)----->   66AK_2 (recover the refclk from received data on the 66AK_2)

         ↑                        

    refclk_1 

    Is it possible?

    Regards.