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AM5718: power down sequence

user6005984
Prodigy 90 points

Part Number: AM5718

about power down sequence

1.According to table.5-3Power-Down Sequencing in AM5718 datasheet,vddshv[1-7,9-11] is allowed to ramp down at 2 point.
How can I decide which one?


2.At sheet5(power) in AM571x Industrial EVM schematic,The following sentences exist,"It has been later determined that the clamp circuit on VSDMMC is not sufficient. Therefore, it is no longer required. The power-down sequence defined in the Data Manual must be met."
Please tell me this in detail.
Now I use TPS659162RGZR for PMIC.Is it not neccesarry to take care this sentences?

  • 0
    TI__Intellectual 1931 points

    User,

    Please refer to note #7 in the Data Manual.

    1. vddshv[1-7,9-11] is allowed to ramp down at 2 different points based on the IO voltage that is being applied. If voltage is 3.3V then it would be in the first ramp down step, if it is 1.8V then it can be ramped down on the second step OR "If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must ensure that the vddshv[1-7,9-11] rail is never higher than 2.0 V above the vdds18v rail."
    2. The clamp circuit is not needed, the PMIC OTP will handle the proper power up and power down sequence. "Note that by default LDO1 is in bypass mode, which means its output is equal to its input. Typically, LDO1 would be supplied by a 3.3-V supply from a preregulator or from the switched 3.3-V output of the load switch enabled by GPIO_0."
    3. The PMIC you have listed is a known PMIC and already configured for use on these SoC devices. So in essence the PMIC will handle the power up and power down of your question #1 and #2. Please refer to the EVM or PMIC user guides for connection mapping.

    Thanks,

    Alec

  • 0 in reply to AJS214
    Prodigy 90 points

    Thank you, Alec.

    I have understood.