DRA829V: Sample Driver for Camera Subsystem/CSI2 RX Interface

Hi Mike,

Can you please check if you have pdk\packages\ti\drv\csirx folder? 

Regards,

Brijesh

Hi Brijesh,

Thank you for the quick reply.  I do not have that folder.  I do see the folder packages/ti/board/diag/csirx/src which contains test code, which looks to exercise the CSI RX interface, but not the driver itself.  Is it possible that I have cloned the wrong git repository?

https://git.ti.com/git/processor-sdk/pdk.git

Thanks

Mike

Hi Mike,

CSIRX driver is not available in this PDK repo. 

Please download and install PSDKRA from .

This will include PDK with CSIRX driver.

Regards,

Brijesh

Hi Brijesh,

Thank you for providing this link.  I built the csirx_capture_test_main.c example.  Unfortunately, we have a proprietary OS, so the port was not easy.  Also, this example uses a Ub953, which I do not have.  The example code does not mention how this device is configured.

I am curious if TI has an APP Note or white paper that I can learn more about the CSI and D-PHY SS.  There is a lot of code in this driver, and the TRM is not documented very well.

My system has 2 ADV7482 ICs connected to CSI-RX0 and CSI-RX1.  (The Ub953 is similar to the ADV7482; it's an HDMI to CSI encoder.)  We are not using CSI-TX.  I need to capture two video formats: 1920x1080p60 and 1920x1080i60.  I like to know how to modify the csirx_capture_test_main.c to work on my platform.  And, if possible, I'd like to know how the Ub953 is configured so that I can configure the ADV7482.

If you could point me to some high-level information, that would be greatly appreciated.

Thanks
Mike

Hi Mike,

This example uses single API App_sensorConfig for configuring SERDES and sensor, so you would require to update this API for you input device. 

In addition, please check the API App_initCaptParams. This API initializes CSI2 parameters. Please update it according to how your device is connected to CSI, eg number of lanes, lane speed, lane polarity etc.. 

Driver provides interface to configure these registers, so we dont really have to update the registers in the application. 

Regards,

Brijesh

Can you help determine the value I should set for DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT0, or possibly point me to documentation that explains the equation?  I see two examples in the PDK: one selects 800-880 and the other 1500-1750.  Neither have any comments to explain why these values are selected.  One of my video inputs has a MIPI clock of 371.5MHz.  I am using 4 lanes.  Do I need to multiply 371.5 x 4 and use the 1350-1500 for a total bandwidth across all lanes?

In other words, is this a per lane setting or an aggregate lane setting?  I am also confused about the right and left band control.

As a reminder, my product is video capture only.  Meaning, I only receive on CSI.  No transmit.

Thanks
Mike

Mike,

This parameter is used to configure lane speed, in terms of mbps and it is per lane configuration.

So if the clock output is 371.5MHz, can we assume the data rate per lane as 743mbps? 

Regards,

Brijesh

Thank you for the explanation. Can I assume that the data rate per lane is the clock rate x2 due to DDR?

I also have the follow up questions for the DPHY configuration.

• How do I set the bandGapTimerVal (O_SSM_WAIT_BGCAL_EN or DPHY_RX_VBUS2APB_CMN0_CMN_DIG_TBIT2[8:1])? I see in the example code the value of 0x14 used. I cannot find any explanation of why 0x14 is selected in the sample code, nor any documentation in the TRM about how to select this value.

• How do I set the psmClkFreqDiv (PSM_CLOCK_FREQ or DPHY_RX_MMR_SLV_LANE[23:16])? I see the example code using a value of 0x53. Comments say that this is a clock divider that sets the PMA state machine clock frequency, which is a function of the “psm_clock”, and should result in a clock frequency of 1MHz.

• I presume that the ”psm_clock” is set by PSM_CLOCK_FREQ (DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT1[8:1])? Correct? In the example driver code, I do not see this register being initialized. It is always zero. Why is this register never initialized?
• If DPHY_RX_VBUS2APB_PCS_TX_DIG_TBIT1[0] is zero, comments say the psm_clock_freq comes from tbit, but it doesn’t say which tbit. Can you help me figure this part out?

• Can you help me figure out the source for the ”psm_clock”? Is it the MIPI Clock In? The MIPI/CSI data rate? The CSI_RX_MAIN_CLK?
• If I reverse engineer the number 0x53 to match a 1MHz PMA state machine clock, that would indicate that the “psm_clock” is 83MHz. I don’t see how 83Mhz fits anywhere in the example code.

Again, thank you for all the help. Very appreciated!

Mike

Hi Mike,

For the rest of the configuration, please use CSIRX driver. They dont really need to change. Only TBIT0 needs to be changed based on the lane speed. 

Yes data rate is 2x the clock rate, since it is DDR.

Could you please use CSIRX driver on R5F for all of these configuration? Driver takes care of programming them correctly. 

Regards,

Brijesh