• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 613 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TDA4VM: TDA4 data

Guoxun
Intellectual 670 points
Part Number: TDA4VM

I want to develop algorithm LBP on TDA4VM.

How should I load data on C71x DSP or C66x DSP?  Is the data loaded with DMA set by me per cycle? Or, the data is automatically loaded by DMA?

That means: Before calculation for every cycle , I should load the corresponding data into L1 cache through DMA(so to main memory and L2)?

Is there an example about TIOVX that show the whole process included load data(from sensor and local memory), data transfer,  calculation of per cycle, get final result ?

For C71x DSP, is there a user manual to introduce the DSP (include cache, instruction, corePac, Optimizing Compiler)?

 

  • 0
    TI__Genius 13845 points

    Hello,

    For your final question, please see the below FAQ for information regarding the C7x DSP.  For your other questions, I will need to consult with a colleague and get back to you.

    Regards,

    Lucas

  • 0 in reply to Lucas Weaver
    Intellectual 670 points

    Thanks, wait for your reply about other questions.

    Is there an example running on C66x DSP?

    I want to know: how does C66x DSP transfer the data including L1 cache, L2 cache and main memory and how to set L1 cache, L2 cache.

    And which file should call the function CACHE_L2SetSize() and when?

  • 0 in reply to Guoxun
    TI__Genius 10355 points

    There is plenty of publicly available documentation on C66 DSP, cache, ISA, compiler, optimization etc.

    Request you to find it online for reference and get familiar with the architecture and programming.

    For example here is a userguide on using C66 cache

    You can set cache sizes using CSL functions while working in baremetal mode. But recommended approach is to use BIOS API's to set cache sizes.

    Also for your reference, there is an entire library of C66 kernels in the SDK under ti-processor-sdk-rtos-j721e-evm-07_02_00_06/vxlib_c66x_1_1_5_0/packages/ti/vxlib/src/vx

    Regards,
    Shyam