Hi,
We designed DM368 board with HDMI(SIL9022aTX) video port . I have configured PRGB 24 bit (RGB888) in VENC driver of davinci_platform. i called that function in the davinci_enc_priv_setmode. I changed configure pin of RGB888 in the davinci_enc_set_prgb function as show below.But i am able red edid from HDTV . but i am unable get display. please suggest me how to this problem and it 640x480 on HDTV.
static void davinci_enc_set_prgb(struct vid_enc_mode_info *mode_info)
{
unsigned int pll_div6;
enableDigitalOutput(1);
dispc_reg_out(VENC_VIDCTL, 0x141);
if (cpu_is_davinci_dm365()) {
/* Setup SYSCLK6 to generate 33MHz */
pll_div6 = __raw_readl(IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x968));
if ( strcmp(mode_info->name,VID_ENC_STD_720P_30) == 0 )
pll_div6 = 0x8000 | 6; /* 486/7= 69.43Mhz */
else
pll_div6 = 0x8000 | 14; /* 486/15 = 32.4Mhz */
__raw_writel(pll_div6, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x968));
/* Set the bit in the ALNCTL register to flag a change in the
* PLLDIV6 ratio */
__raw_writel(1<<6, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x940));
/* Run a GO operation to perform the change. */
__raw_writel(0x1, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x938));
}
/* set VPSS clock */
__raw_writel(0x18, IO_ADDRESS(SYS_VPSS_CLKCTL));
dispc_reg_out(VENC_DCLKCTL, 0);
dispc_reg_out(VENC_DCLKPTN0, 0);
/* Set the OSD Divisor to 1. */
dispc_reg_out(VENC_OSDCLK0, 0);
dispc_reg_out(VENC_OSDCLK1, 1);
/* Clear composite mode register */
dispc_reg_out(VENC_CVBS, 0);
/* Set PINMUX1 to enable all outputs needed to support RGB666 */
if (cpu_is_davinci_dm355()) {
/* Enable the venc and dlcd clocks. */
dispc_reg_out(VENC_CLKCTL, 0x11);
davinci_cfg_reg(DM355_VOUT_FIELD_G70);
davinci_cfg_reg(DM355_VOUT_COUTL_EN);
davinci_cfg_reg(DM355_VOUT_COUTH_EN);
} else if (cpu_is_davinci_dm365())
{
/* DM365 pinmux */
dispc_reg_out(VENC_CLKCTL, 0x11);
#if 0
davinci_cfg_reg(DM365_VOUT_B0);
davinci_cfg_reg(DM365_VOUT_B1);
davinci_cfg_reg(DM365_VOUT_B2);
davinci_cfg_reg(DM365_VOUT_G0);
davinci_cfg_reg(DM365_VOUT_G1);
davinci_cfg_reg(DM365_VOUT_R0);
davinci_cfg_reg(DM365_VOUT_R1);
davinci_cfg_reg(DM365_VOUT_R2);
davinci_cfg_reg(DM365_VOUT_COUTL_EN);
davinci_cfg_reg(DM365_VOUT_COUTH_EN);
davinci_cfg_reg(DM365_VOUT_LCD_OE);
#endif
//HDMI Venkat
//0x145555
printk(" \nVenkat pin configure HDMI\n");
davinci_cfg_reg(DM365_VOUT_HVSYNC);
davinci_cfg_reg(DM365_VOUT_LCD_OE);
davinci_cfg_reg(DM365_VENC_VCLK);
davinci_cfg_reg(DM365_GIO27_B0);
davinci_cfg_reg(DM365_GIO28_B1);
davinci_cfg_reg(DM365_CPU_EXTCLK_B2);
davinci_cfg_reg(DM365_COUT0_B3);
davinci_cfg_reg(DM365_COUT1_B4);
davinci_cfg_reg(DM365_COUT2_B5);
davinci_cfg_reg(DM365_COUT3_B6);
davinci_cfg_reg(DM365_COUT4_B7);
davinci_cfg_reg(DM365_GIO29_G0);
davinci_cfg_reg(DM365_GIO30_G1);
davinci_cfg_reg(DM365_COUT5_G2);
davinci_cfg_reg(DM365_COUT6_G3);
davinci_cfg_reg(DM365_COUT7_G4);
davinci_cfg_reg(DM365_GIO32_R0);
davinci_cfg_reg(DM365_GIO33_R1);
davinci_cfg_reg(DM365_CPU_FIELD_R2);
osd_write_left_margin(mode_info->left_margin);
osd_write_upper_margin(mode_info->upper_margin);
} else {
dispc_reg_out(VENC_CMPNT, 0x100);
davinci_cfg_reg(DM644X_GPIO46_47);
davinci_cfg_reg(DM644X_GPIO0);
davinci_cfg_reg(DM644X_RGB666);
davinci_cfg_reg(DM644X_LOEEN);
davinci_cfg_reg(DM644X_GPIO3);
}
osd_write_left_margin(mode_info->left_margin);
osd_write_upper_margin(mode_info->upper_margin);
/* Set VIDCTL to select VCLKE = 1,
VCLKZ =0, SYDIR = 0 (set o/p), DOMD = 0 */
dispc_reg_merge(VENC_VIDCTL, 1 << VENC_VIDCTL_VCLKE_SHIFT,
VENC_VIDCTL_VCLKE);
dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_VCLKZ_SHIFT,
VENC_VIDCTL_VCLKZ);
dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_SYDIR_SHIFT,
VENC_VIDCTL_SYDIR);
dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_YCDIR_SHIFT,
VENC_VIDCTL_YCDIR);
dispc_reg_merge(VENC_DCLKCTL,
1 << VENC_DCLKCTL_DCKEC_SHIFT, VENC_DCLKCTL_DCKEC);
dispc_reg_out(VENC_DCLKPTN0, 0x1);
davinci_enc_set_display_timing(mode_info);
dispc_reg_out(VENC_SYNCCTL,
(VENC_SYNCCTL_SYEV |
VENC_SYNCCTL_SYEH | VENC_SYNCCTL_HPL
| VENC_SYNCCTL_VPL));
/* Configure VMOD. No change in VENC bit */
//dispc_reg_out(VENC_VMOD, 0x2011);
dispc_reg_out(VENC_VMOD, 0x2010);
//dispc_reg_out(VENC_LCDOUT, 0x1);
}
it need it to enable vencoder in VMOD registers.
Thanks
venkat