• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 99 subscribers
  • Views 889 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

McBSP as slave (6437 controller) with "Spectrum digital" EVM board not working..

Kanthi Uppala
Prodigy 90 points

Hello,

     I would like to have SPI communication between Freescale S12X(Master ) & TI (6437) as slave.

    I have configured TI as mentioned in the McBSP User's Manual Guide for SPI slave operation. 

    the sample code i have generated is using "pspdrivers_1_10_03".

     I am sure the Master is working correctly because I have already tested the Master & Slave with both Freescale boards. But when I use TI 6437 evaluation board the problems appear.

    I am using the Socketed EEPROM pins (in the 6437 EVM) for connecting the wires from Master to slave.

   I guess the problems are with the configuration of 6437.

The below is the program:

As data recieved by me in DRR register is totally erroneous & mostly constant (like 1F, 3F & 7F sometimes FF) these are the data's i recieve for what ever i send from master.

The master is working at 1Mhz. So I have just made the CLKGDV =1

The GEL file used in 1.50 version the latest one.

It says the speed is 594 Mhz, to cross check this,  I configured the 6437 as master to check the ouptut clock with various CLKGDV values, The clock coming from  McBSP module (CLKX pin) is around 100Mhz... roughly 102Mhz...

One more my concern is there is no application note for McBSP as slave from TI, most of the configuraitons are McBSP as master with SPI EEPROM. I request TI to create one application note where McBSP is used a SPI Slave & master being other controller (TI or any other controller).

 

int main (void) 

{

  //enable mcbsp0 in power and sleep controller

  device_init(); 

 

  //setup mcbsp registers and start mcbsp running 

  Init_McBsp_SPI();

 

  Reset_McBSP_SPI();

 

  Configure_McBSP_SPI_Slave();

 

  Set_McBSP_SPI();

 

  //test loopback, returns 0 for pass and 1 for fail 

  while(1)

  {

    McBSP_SPI_Recieve_Byte();

  }

}

 

void Init_McBsp_SPI(void)

{

mcbspRegs->SPCR = CSL_MCBSP_SPCR_RESETVAL;

mcbspRegs->RCR  = CSL_MCBSP_RCR_RESETVAL;

mcbspRegs->DRR  = CSL_MCBSP_DRR_RESETVAL;

mcbspRegs->DXR  = CSL_MCBSP_DXR_RESETVAL;

mcbspRegs->XCR  = CSL_MCBSP_XCR_RESETVAL;

mcbspRegs->SRGR = CSL_MCBSP_SRGR_RESETVAL;

mcbspRegs->PCR  = CSL_MCBSP_PCR_RESETVAL;

}
void Reset_McBSP_SPI(void)
{
CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_RRST,DISABLE);    //receiver enable
CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_XRST,DISABLE);    //transmitter enable
CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_GRST,RESET);      //SRGR out of reset
}
void Set_McBSP_SPI(void)
{
//start the mcbsp running
CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_RRST,ENABLE);    //receiver enable
CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_XRST,ENABLE);    //transmitter enable
CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_GRST,CLKG);      // SRGR out of reset
}
void Configure_McBSP_SPI_Slave(void)
{
  // Configurtation for SPCR Registers
CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_CLKSTP,DELAY);  //configure CLKSTP to 11 (phase)
CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_XINTM,XRDY); // configure the Tx intrpt for FRM synch.. which is not implemented.
    CSL_FINST(mcbspRegs->SPCR,MCBSP_SPCR_RINTM,RRDY); // configure the Rx intrpt for RRDY.. which is already implemented.
// Configurtation for PCR Registers
CSL_FINST(mcbspRegs->PCR,MCBSP_PCR_CLKXP,RISING ); // CLXP = 0 (polarity - CPOL)
CSL_FINST(mcbspRegs->PCR,MCBSP_PCR_CLKXM,INPUT); // Driven by Master (CLKX pin)
CSL_FINST(mcbspRegs->PCR,MCBSP_PCR_FSXM,EXTERNAL); // Driven by Master (SS pin)
CSL_FINST(mcbspRegs->PCR,MCBSP_PCR_FSXP,ACTIVELOW); // Active low since its input
CSL_FINST(mcbspRegs->PCR,MCBSP_PCR_SCLKME,NO); // Input Driven by master (Clock)
// Configurtation for SRGR Registers
CSL_FINST(mcbspRegs->SRGR,MCBSP_SRGR_CLKSM,INTERNAL); // for slave config
CSL_FINST(mcbspRegs->SRGR,MCBSP_SRGR_CLKGDV,RESETVAL); // to divide by 2 for slave config
// Configurtation for XCR Registers
CSL_FINST(mcbspRegs->XCR,MCBSP_XCR_XPHASE,SINGLE_FRM); // only 1 frame (SPI compliant)
CSL_FINST(mcbspRegs->XCR,MCBSP_XCR_XWDLEN1,8BIT); // 8 bits of transfer length
CSL_FINST(mcbspRegs->XCR,MCBSP_XCR_XFRLEN1,RESETVAL); // 1 word per tx frame
CSL_FINST(mcbspRegs->XCR,MCBSP_XCR_XDATDLY,0BIT); // for slave configuration(impt one)
// Configurtation for RCR Registers
CSL_FINST(mcbspRegs->RCR,MCBSP_RCR_RPHASE,SINGLE_FRM); // only 1 frame (SPI compliant)
CSL_FINST(mcbspRegs->RCR,MCBSP_RCR_RWDLEN1,8BIT); // 8 bits of transfer length
CSL_FINST(mcbspRegs->RCR,MCBSP_RCR_RFRLEN1,RESETVAL); // 1 word per tx frame
CSL_FINST(mcbspRegs->RCR,MCBSP_RCR_RDATDLY,0BIT); // for slave configuration(impt one)
}
void McBSP_SPI_Recieve_Byte(void)
{
while(CSL_FEXT(mcbspRegs->SPCR,MCBSP_SPCR_RRDY)
             != CSL_MCBSP_SPCR_RRDY_YES)
    {
             ;
    }
}