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TDA4VM: What are the timing requirements for mipi signals for csirx and csitx?

buaawkp
Expert 1345 points
Part Number: TDA4VM

Hi，

I am currently debugging the csirx interface. I can read the signal from the mipi signal of csirx, but the capture module does not receive any data. I suspect that the timing of mipi is not matched. Therefore, I have the following questions.

What are the requirements of the CSIRX port for the following parameters of the mipi signal? What registers can be used to configure these parameters? Where can I get this information:

1. Ths_settle;

2. Ths-lpx;

3. Ths-trail;

Similarly, what are the timing parameters of the mipi signal of csitx?

1. Ths_prepare;

2. Ths_zero;

3. Ths_lpx;

4. Ths_zero;

Thanks

Kepei

  • 0
    TI__Genius 10180 points

    Kepei,

    The timings are set automatically once you program the target data rate into TX_DIG_TBIT0 (0x04580B00).  Please program the value corresponding to the speed rate you are interfacing in into the [9:5] and [4:0] bit fields of this register.

    If you still have issues, please dump DPHY register status (0x045800000, 0x04581000), size: 0x3e8

      1. Correct lane speed should be programmed into TX_DIG_TBIT0
      2. Make sure resistor calibration sequence was done (TBIT58 - 0x045800F8 [0] = 1)
      3. Make sure data lane polarity match board connection

    Best Regards,

    Shiou Mei