Other Parts Discussed in Thread: AMIC110
Hi Team,
In order to configure the DDR on a custom board we are following the " Board porting up using Processor SDK RTOS for AM335x/AMIC110" document
, that is supposed to be the same for both am437x and am335x.
In this document , there is a link to the DDR setup procedure https://www.ti.com/lit/an/sprack4/sprack4.pdf?ts=1611505388302
/** \brief IDK EVM DDR3 configuration */
static const sblPlatformDdrCfg_t IDKEVM_DDR3_CONFIG =
{
{
DDR3_CONTROL_DDR_ADDRCTRL_IOCTRL_VALUE, /* ddr address io control */
DDR3_CONTROL_DDR_DATA_IOCTRL_VALUE, /* ddr data io control */
IDKEVM_DDR3_CONTROL_EMIF_SDRAM_CONFIG_EXT_VALUE /* emif sdram config ext */
}, /* ddrCtrl_t */
{
IDKEVM_DDR3_EMIF_DDR_PHY_CTRL_VALUE, /* ddr phy control */
IDKEVM_DDR3_EMIF_SDRAM_TIM_1_VALUE, /* sdram timing1 */
IDKEVM_DDR3_EMIF_SDRAM_TIM_2_VALUE, /* sdram timing2 */
IDKEVM_DDR3_EMIF_SDRAM_TIM_3_VALUE, /* sdram timing3 */
IDKEVM_DDR3_EMIF_SDRAM_CONFIG_VALUE, /* sdram config */
IDKEVM_DDR3_EMIF_SDRAM_REF_CTRL_VALUE, /* sdram ref control */
DDR3_ZQ_CONFIG_VALUE /* ZQ config */
}, /* ddrEmif_t */
{
DDR3_PHY_GATELVL_INIT_RATIO, /* Phy Gate level init ratio. */
IDKEVM_DDR3_PHY_WR_DQS_SLAVE_RATIO, /* wr dqs slave ratio */
IDKEVM_DDR3_PHY_FIFO_WE_SLAVE_RATIO, /* fifo we slave ratio */
DDR3_PHY_USE_RANK0_DELAYS /* use rank0 delay */
} /* ddrEmifPhy_t */
};
at the sbl_am43xx_platform_ddr.c file ?
