TDA2HG: How to make DDR access more efficient

Part Number: TDA2HG

Hi,

We have only one EMIF with DDR3L. But DDR bandwidth is hit the top(2.4GB/s) and slow down my GPU render fps(14fps).

After some optimise of DDR bandwidth, I make GPU render fps more than 17fps. But I notice DDR bandwidth is only 2.1GB/s.

And I checked document "TDA2xx and TDA2ex Performance" it said EDMA transfer from EMIF to EMIF can have 3.2GB/s.

Now my initors bandwidth is below:

EDMA: 277MB/s, GPU: 1120MB/s, DSS: 259MB/s, MPU: 224MB/s, IVA: 240MB/s

I used regulator on IVA, since it is only initiator I can reduce priority. But I hope the total bandwidth can rich 2.4GB/s as it used be.

So do you have any suggection to optimise DDR access method?

Thanks!

BR/Tim