MCBSP SPI mode DX pin Output Enable Delay

Alphan Karacaer56

Hello I am trying to run SPI communication in 50 MHz in our custom designed board based on EMV 6474.

I've encountered a problem, DSP drives DX (MOSI) pin 10 ns later than clock falling edge, only in the first bit, so when the slave always reads first bit as 0. When the rate is above 50 MHz, like 25 MHz, 10 ns delay is not a problem, because clock pulses are wide enough to tolerate 10 ns delay.

If I want to run go 50 MHz, I have to communicate 31 bit in this case, the first bit is always 0. Is there any way to overcome this problem.

Should I have to setup my communication block over 32 bit if I want 50MHz

Thanks

Alphan

over 14 years ago

0 nmin Wu over 14 years ago

TI__Intellectual 910 points

Alphan,

based on your description, it seems that you are using the following configuration for Mcbsp as SPI. Right?

CLKSTP = 10b, CLKXP = 1

You may try to use different configurations such as CLKSTP = 11b, CLKXP = 1 to overcome the problem.

Please refer to the datamanual for the timings for different configuration.

regards,

yanmin

0 Alphan Karacaer56 over 14 years ago in reply to nmin Wu

Intellectual 835 points

Hello,

I have tried all combinations but no matter I've done, in the first bit there is always a delay more than 10ns.

Is it possible to produce 33 clock cycles for 32 bit communication, otherwise we have to use a 31 bit format for our communication bus.

Thanks

Alphan

0 nmin Wu over 14 years ago in reply to Alphan Karacaer56

TI__Intellectual 910 points

Alphan,

it is impossible to produce 33 clock cycles for 32 bit communication.

regards,

yanmin

0 Alphan Karacaer56 over 14 years ago in reply to nmin Wu

Intellectual 835 points

OK thank you very much for your interest.

Alphan

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MCBSP SPI mode DX pin Output Enable Delay