Sitara Support Team,
My customer is using an HDMI receiver (ADV7611) connected to port_A of VIP on a custom board
with AM5728 to capture HDMI signal with gstreamer.
S/W: Linux SDKv4.1.0.6
I have two questions about the following phenomenon, and would appreciate your answers.
Sometimes, the following log is generated.
[2021-01-27 20:52:53.747] [ 3035.293646] vip1-s0: VIP_PORTA_OUTPUT_FIFO_YUV
[2021-01-27 20:52:53.747] [ 3035.298859] vip1-s0: vip_overflow_recovery_work: Port A
The log is output five times as a set, and the frequency of occurrence is indeterminate: some occur immediately after startup,
some occur every second after a while, and some occur 25 minutes after startup.
The frequency of occurrence is not fixed.
The problem occurs when I start gstreamer with the following parameters.
==============================================================================================================
gst-launch-1.0 v4l2src device=/dev/video1 io-mode=4 ! tee name=s s. ! queue ! vpe ! video/x-raw,format=NV12,width=1280,height=720 ! waylandsink use-drm=true sync=false s. ! queue ! vpe ! videorate ! video/x-raw,format=NV12,width=640,height=360,framerate=4/1 ! ducatijpegenc ! multifilesink max-files=1 location=/tmp/html/data/HDMIinput.jpg sync=false s. ! queue ! vpe ! video/x-raw,format=NV12,width=960,height=540 ! videorate max-rate=15 drop-only=true ! ducatih264enc intra-interval=60 bitrate=512 rate-preset=1 ! h264parse ! rtph264pay ! udpsink host=172.31.11.1 port=31020 sync=false
==============================================================================================================
The customer investigated and found that the output was generated by handle_parser_irqs() in the VIP driver (drivers/media/platform/ti-vpe/vip.c), and checking the factors, it was found that bit4 of the VIP_FIQ_STATUS register in the VIP Parser; the OUTPUT_FIFO_PRTA_LUMA_STATUS of VIP_FIQ_STATUS register of VIP Parser was set to "1".
Question 1
Can you please confirm the conditions under which the above bit is set to 1?
We think that the video data sent from the HDMI receiver is DMA-transferred
by VPDMA via VIP port_A, but the VPDMA memory transfer does not arrive
in time and the FIFO on the VIP side overflows.
Question 2
In the description of bit4 of VIP_FIQ_STATUS register of VIP Parser; OUTPUT_FIFO_PRTA_LUMA_STATUS,
there is "Output FIFO Port A Luma Overflow Status". Is it correct that this Output FIFO is the FIFO
between the Port_A side of the VIP Parser and the VPDMA?
Please let me know if there are any other information you need to verify.
Best regards,
Kanae