AM6548: AM65X A53 reset request from R5 SPL to DMSC

Ravikiran J J

Part Number: AM6548

Hi,

We are working on AM65X EVM board.

As per our understanding R5 SPL is the one responsible for tispl.bin load to memory and A53 cores reset by requesting the same to the DMSC core.

We are going through the AM65X u-boot source code for R5 SPL to understand the A53 reset request to the DMSC.

board_init_f() function defined in the arch/arm/mach-k3/am6_init.c file

board_init_r() function defined in the common/spl/spl.c file

jump_to_image_no_args() function defined the arch/arm/mach-k3/common.c

R5 core release resource ( release_resources_for_core_shutdown() ) and going to low power state / WFE code is present in the function jump_to_image_no_args().

But, reset of the A53 core code presence, is not clear in the R5 SPL code sequence

Could anyone please indicate which part of R5 SPL code is responsible for the A53 core reset ?

Thanks and Regards,

Ravikiran J J

over 4 years ago

0 Keerthy J over 4 years ago

TI__Guru**** 163290 points

Hi Ravikiran,

File in u-boot directory: arch/arm/mach-k3/common.c

Function: jump_to_image_no_args

ret = rproc_init();
        if (ret)
                panic("rproc failed to be initialized (%d)\n", ret);

        init_env();
        if (!fit_image_info[IMAGE_ID_DM_FW].image_start)
                size = load_firmware("mcur5f0_0fwname", "mcur5f0_0loadaddr",
                                     &loadaddr);

        /*
         * It is assumed that remoteproc device 1 is the corresponding
         * Cortex-A core which runs ATF. Make sure DT reflects the same.
         */
        if (!fit_image_info[IMAGE_ID_ATF].image_start)
                fit_image_info[IMAGE_ID_ATF].image_start =
                        spl_image->entry_point;

        ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
        if (ret)
                panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);

        /* Add an extra newline to differentiate the ATF logs from SPL */
        printf("Starting ATF on ARM64 core...\n\n");

        ret = rproc_start(1);
        if (ret)
                panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);

The above code snippet is R5 SPL initializing a53. Gets it out of reset and loads ATF(ARM trusted firmware). Hope this
is what you are looking for.

Please resolve the issue.

Best Regards,
Keerthy

0 Ravikiran J J over 4 years ago in reply to Keerthy J

Intellectual 640 points

Hi Keerthy,

Thank you so much for the A53 core reset and firmware load code snippet.

Further we are trying to understand the A53 core reset from R5 SPL.

Our understanding as follows:

1. R5 U-boot SPL has A53 rproc driver to initialize the A53 core and R5 DTS has A53 core 0 entry with all the details required for rproc driver

2. R5 U-Boot SPL getting the A53 core out of reset by sending request to DMSC SYSFW over TISCI protocol in ti_sci reset driver

Is our above understanding correct for the A53 core reset from R5 SPL ?

Following function/ops call debug prints from the A53 rproc driver and reset-ti-sci driver

Files in U-Boot directory:

drivers/remoteproc/ti_k3_arm64_rproc.c

drivers/reset/reset-ti-sci.c

Function calls debug prints flow:

k3_arm64_probe
k3_arm64_of_to_priv

reset_get_by_index.......

ti_sci_reset_probe(dev=41c25ed4)
ti_sci_reset_of_xlate(rst=41c6d300, args_count=2)
ti_sci_reset_of_xlate..............[2]rst->id202......rst->data0
ti_sci_reset_request(rst=41c6d300)
ti_sci_proc_of_to_priv
k3_arm64_init

Once k3_arm64_of_to_priv() function calls reset_get_by_index()

Its leading to call ti_sci_reset_probe ->ti_sci_reset_of_xlate (setting the device ID and reset mask) -> ti_sci_reset_request

We observed the call ti_sci_reset_request() function in the reset-ti-sci driver and it is currently a dummy call.

static int ti_sci_reset_request(struct reset_ctl *rst)
{
debug("%s(rst=%p)\n", __func__, rst);
return 0;
}

Then how exactly A53 reset request sent from R5 U-boot SPL code to DMSC over TISCI protocol ?

Thank you in advance for looking into this.

Thanks and Regards,

Ravikiran J J

0 Keerthy J over 4 years ago in reply to Ravikiran J J

TI__Guru**** 163290 points

Hi Ravikiran,

static int k3_arm64_start(struct udevice *dev)
{
struct k3_arm64_privdata *rproc = dev_get_priv(dev);
int ret;

dev_dbg(dev, "%s\n", __func__);

ret = power_domain_on(&rproc->gtc_pwrdmn);
if (ret) {
dev_err(dev, "power_domain_on() failed: %d\n", ret);
return ret;
}

/* Enable the timer before starting remote core */
writel(GTC_CNTR_EN, rproc->gtc_base + GTC_CNTCR_REG);

/*
* Setting the right clock frequency would have taken care by
* assigned-clock-rates during the device probe. So no need to
* set the frequency again here.
*/
ret = power_domain_on(&rproc->rproc_pwrdmn);
if (ret) {
dev_err(dev, "power_domain_on() failed: %d\n", ret);
return ret;
}

return ti_sci_proc_release(&rproc->tsp);
}

/**
* ti_sci_proc_release() - Release a physical processor control
*
* @proc_id: Processor ID this request is for
*
* Return: 0 if all goes well, else appropriate error message
*/
int ti_sci_proc_release(uint8_t proc_id)
{

Thea above 2 call sequence enables A53 processor.

Hope it answers your question. Please resolve if no further questions.

Best regaards,
Keerthy

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AM6548: AM65X A53 reset request from R5 SPL to DMSC