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TDA4VM: TDA4 - IPC SPI Master Slave Application

chun chu1
Intellectual 330 points

Part Number: TDA4VM

Hi Sir,

I want to use MCSPI4(MCU 2_1 TI-RTOS) to communicate with MCU_MCSPI2(MCU 1_0 TI-RTOS).
I have a sample program for the A72 TI-RTOS system, but I want to change this example to MCU2_1. Is this feasible?

MCUSW: IPC SPI Master Slave Application

In addition, according to the application of our product, we hope that the Slave can also actively inform the Master that there is data to send. Can you provide a good way? For example, internally connected IO?

SDK: PSDK 7.0.0

Main domain R5F MCU2_1 : TI-RTOS system : SPI Slave

MCU domain R5F MCU1_0 : TI-RTOS system : SPI Master

  • 0
    TI__Mastermind 37435 points

    Hi,

    Yes, you can build MCSPI apps for MCU cores.

    • Have you taken a look at the MCSPI applications provided along with the PDK ? You can adapt them for your requirements. To see them, go to pdk/packages/ti/build, give the command make help and look for the keyword mcspi or MCSPI.
    • To communicate between the cores natively without external wiring, you can use the IPC example applications. To see them go to go to pdk/packages/ti/build, give the command make help and look for the keyword ipc or IPC

    Regards

    Vineet

  • 0 in reply to Vineet Roy
    Intellectual 330 points

    Hi Vineet,

    I want to use MAIN Domain MCU2_1 to enable MCSPI4(Slave) & MCSPI3(Master),

    and use MCU Domain MCU1_0 to enable MCU_MCSPI2(Master) & MCU_MCSPI1(Slave).

    But I refer to the \psdk_rtos\pdk_jacinto_07_00_00\packages\ti\drv\spi\soc\j721e\SPI_soc.c file as follows:

    SPI configuration structure cannot enable MCSPI4(slave) and MCSPI3(master) of MCU2_1 in the MAIN domain.

    Can MCSPI in MAIN domain be enabled only on MPU, but not on MCU2_1?

    /* SPI configuration structure */

    SPI_v1_HWAttrs spiInitCfg[CSL_MCSPI_PER_CNT] =

    {

        {

    #if defined (BUILD_MPU)

            /* main domain */

            (uint32_t)CSL_MCSPI0_CFG_BASE,                         /* baseAddr */

            CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCSPI0_INTR_SPI_0,  /* intNum */

    #else

            /* mcu domain */

            (uint32_t)CSL_MCU_MCSPI0_CFG_BASE,

            CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCSPI0_INTR_SPI_0,

    #endif

            0,                                  /* eventId */

            (uint32_t)SPI_PINMODE_4_PIN,        /* pinMode */

            MCSPI_CHANNEL_0,                    /* chNum */

            MCSPI_SINGLE_CH,                    /* chMode */

            (bool)true,                         /* enableIntr */

            48000000,                           /* inputClkFreq */

            MCSPI_INITDLY_0,                    /* initDelay */

            MCSPI_RX_TX_FIFO_SIZE,              /* rxTrigLvl */

            MCSPI_RX_TX_FIFO_SIZE,              /* txTrigLvl */

            {

                {

                    MCSPI_CS_POL_LOW,                  /* csPolarity */

                    MCSPI_DATA_LINE_COMM_MODE_7,       /* dataLineCommMode */

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,   /* tcs */

                    MCSPI_TX_RX_MODE,                  /* trMode */

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

            },

    #if defined (BUILD_MPU)

            CSL_PDMA_CH_MAIN_MCSPI0_CH0_RX,     /* rxDmaEventNumber */

            CSL_PDMA_CH_MAIN_MCSPI0_CH0_TX,     /* txDmaEventNumber */

    #else

            CSL_PDMA_CH_MCU_MCSPI0_CH0_RX,      /* rxDmaEventNumber */

            CSL_PDMA_CH_MCU_MCSPI0_CH0_TX,      /* txDmaEventNumber */

    #endif

            0,                                  /* edmaTxTCC */

            0,                                  /* edmaRxTCC */

            0,                                  /* edmaTxTC */

            0,                                  /* edmaRxTC */

            NULL,                               /* edmaHandle */

            (bool)false,                        /* dmaMode */

            NULL                                /* dmaInfo */

        },

        {

    #if defined (BUILD_MPU)

            /* main domain */

            (uint32_t)CSL_MCSPI1_CFG_BASE,

            CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCSPI1_INTR_SPI_0,

    #else

            /* mcu domain */

            (uint32_t)CSL_MCU_MCSPI1_CFG_BASE,

            CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCSPI1_INTR_SPI_0,

    #endif

            0,

            (uint32_t)SPI_PINMODE_4_PIN,

            MCSPI_CHANNEL_0,

            MCSPI_SINGLE_CH,

            (bool)true,

            48000000,

            MCSPI_INITDLY_0,

            MCSPI_RX_TX_FIFO_SIZE,

            MCSPI_RX_TX_FIFO_SIZE,

            {

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

            },

    #if defined (BUILD_MPU)

            CSL_PDMA_CH_MAIN_MCSPI1_CH0_RX,

            CSL_PDMA_CH_MAIN_MCSPI1_CH0_TX,

    #else

            CSL_PDMA_CH_MCU_MCSPI1_CH0_RX,

            CSL_PDMA_CH_MCU_MCSPI1_CH0_TX,

    #endif

            0,

            0,

            0,

            0,

            NULL,

            (bool)false,

            NULL

        },

        {

    #if defined (BUILD_MPU)

            /* main domain */

            (uint32_t)CSL_MCSPI2_CFG_BASE,

            CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCSPI2_INTR_SPI_0,

    #else

            /* mcu domain */

            (uint32_t)CSL_MCU_MCSPI2_CFG_BASE,

            CSLR_MCU_R5FSS0_CORE0_INTR_MCU_MCSPI2_INTR_SPI_0,

    #endif

            0,

            (uint32_t)SPI_PINMODE_4_PIN,

            MCSPI_CHANNEL_0,

            MCSPI_SINGLE_CH,

            (bool)true,

            48000000,

            MCSPI_INITDLY_0,

            MCSPI_RX_TX_FIFO_SIZE,

            MCSPI_RX_TX_FIFO_SIZE,

            {

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

            },

    #if defined (BUILD_MPU)

            CSL_PDMA_CH_MAIN_MCSPI2_CH0_RX,

            CSL_PDMA_CH_MAIN_MCSPI2_CH0_TX,

    #else

            CSL_PDMA_CH_MCU_MCSPI2_CH0_RX,

            CSL_PDMA_CH_MCU_MCSPI2_CH0_TX,

    #endif

            0,

            0,

            0,

            0,

            NULL,

            (bool)false,

            NULL

        },

        {

    #if defined (BUILD_MPU)

            /* main domain */

            (uint32_t)CSL_MCSPI3_CFG_BASE,

            CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCSPI3_INTR_SPI_0,

    #else

            /* mcu domain */

            0,

            0,

    #endif

            0,

            (uint32_t)SPI_PINMODE_4_PIN,

            MCSPI_CHANNEL_0,

            MCSPI_SINGLE_CH,

            (bool)true,

            48000000,

            MCSPI_INITDLY_0,

            MCSPI_RX_TX_FIFO_SIZE,

            MCSPI_RX_TX_FIFO_SIZE,

            {

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

            },

            CSL_PDMA_CH_MAIN_MCSPI3_CH0_RX,

            CSL_PDMA_CH_MAIN_MCSPI3_CH0_TX,

            0,

            0,

            0,

            0,

            NULL,

            (bool)false,

            NULL

        },

        {

    #if defined (BUILD_MPU)

            /* main domain */

            (uint32_t)CSL_MCSPI4_CFG_BASE,

            CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCSPI4_INTR_SPI_0,

    #else

            /* mcu domain */

            0,

            0,

    #endif

            0,

            (uint32_t)SPI_PINMODE_4_PIN,

            MCSPI_CHANNEL_0,

            MCSPI_SINGLE_CH,

            (bool)true,

            48000000,

            MCSPI_INITDLY_0,

            MCSPI_RX_TX_FIFO_SIZE,

            MCSPI_RX_TX_FIFO_SIZE,

            {

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

                {

                    MCSPI_CS_POL_LOW,

                    MCSPI_DATA_LINE_COMM_MODE_7,

                    MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY,

                    MCSPI_TX_RX_MODE,

                },

            },

            CSL_PDMA_CH_MAIN_MCSPI4_CH0_RX,

            CSL_PDMA_CH_MAIN_MCSPI4_CH0_TX,

            0,

            0,

            0,

            0,

            NULL,

            (bool)false,

            NULL

        },

    };

  • 0 in reply to chun chu1
    Prodigy 170 points

    Hi ， 

    I also have this need, have you found a solution？

  • 0 in reply to jie xu1
    TI__Mastermind 37435 points

    Hi,

    Sorry for the delay.

    MCSPI is supported on main domain as well. Refer to this thread

    If you want to run on MPU then you need to use Linux. Check this E2E

    Regards

    Vineet