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C6747 HPI host access to L2, EMIFB and Shared RAM

Gaston Schelotto
Expert 2850 points

Hello,

When I perform a busy wait in my C6747 application as follows:

foo = 1;
while(foo);

and then access to the foo variable through HPI (write to 0) in order to exit the loop, I observe this:

  1. If foo is placed in internal RAM L2, HPI write access works fine and foo is changed to 0.
  2. If the variable is placed in SDRAM (EMIFB), HPI does not able to change the value (foo remains 1).
  3. Same than point 2. when the variable is placed in Shared RAM (128KB).

In the last two points, although the variable has not been written, I able to check HPIAW with the right address value. It seems a privilege/priority/permission issue in order HPI to access to different memory locations while CPU is accessing too. Is there any way to change this configuration?

Regards,
Gaston

  • 0
    TI__Guru* 84110 points

    Gaston,

    This should actually be in the C67x Forum, but I will make some comments before it gets moved.

    You are probably experiencing "cache coherency" issues. If the external location in SDRAM or SL2RAM is cached, then the processor will read it once into the cache, and then the cache hardware will make the value be read from the cache every time after that. The HPI will write to the physical memory that has already been cached, and the cache will still report the old value.

    You can turn caching off with a MAR bit, but that turns cache off for 16MB of memory address range.

    You can do a manual cache-invalidate command in the while (foo) loop so that each read will return a new value from the physical memory. Keep in mind that this will invalidate an entire cache line, so you will want to make sure you take precautions for the rest of your code.

    Regards,
    RandyP

     

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