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TMS320C6746: SPI Data Format Registers (SPIFMTn)

Lakhwinder Singh
Intellectual 740 points
Part Number: TMS320C6746


Hii,

can anyone please clear the purpose of  SPI Data Format Registers (SPIFMTn) in TMS320C6746

I want to configure the SPI for interfacing with ADC ADS8588 as below

-TMS320C6746 in Master mode

- to capture data on falling edge of clock

- default clock polarity is low when idle, when leading edge is rising edge, trailing edge is falling edge 

- speed 1Mhz

- ADC is connected to chip select 0  of TMS320C6746, which i want to control using gpio by configuring cs0 as gpio

using external oscillator 24Mhz

can anyone please guide me

  • 0
    TI__Mastermind 28235 points

    I’ll see if I can help you here on the understanding of the SPI register.

     

    WDELAY can be used to create a delay between transmissions. Not sure you’ll need this.

    PARPOL is the polarity of parity bit appended to the end of each transmission. This will be a don’t care for you

    PARENA enables the generation/checking of the parity bit. The ADC does not support parity so this should be disabled.

    WAITENA is used to honor a flow control signal from the ADC. It’s possible you could use the ADC busy signal here.

    SHIFTDITR control which bit of the data word is transmitted first. Looks like the ADC will send MSB first.

    DISCSTIMERS allows for delays to be inserted when communicating with multiple peripherals use the same SPI interface. If you are only connected to the ADC then this is not necessary

    POLARITY controls the active state of the CS line – don’t care if you are using GPIO.

    PHASE Controls the clock phase relative the top the data. I believe you want to use half clock cycle mode (1).

    PRESCALE – used to determine the SPI clock frequency. You will program this to achieve your 1MHz target. 

    CHRLEN is used to set the size of the data word in the transmission – The ADC will transmit 16 bits (10h)

    --Paul

  • 0 in reply to PaulM
    Intellectual 740 points

    Hi, 

    Thanks paul,

    but why there are four such registers and which one write for these settings 

    there are mulitple SPIFMTn registers

  • 0 in reply to Lakhwinder Singh
    TI__Mastermind 28235 points

    Each SPIFMTn register can be set to different formats so that peripherals having different format requirements can be connected to the same SPI interface. 

    You can select which SPIFMT to use by programming the DFSEL field in the SPIDAT1 register. 

  • 0 in reply to PaulM
    Intellectual 740 points

    Hi,

    thanks, issue resolved