A problem of dm365 LCD display

fb0 image(first) is on which display?  is it also on lcd?  Looks like [referring to second image] feature similar to 'rotation' is enabled. Have to enabled any such feature? 

I get data form the /dev/fb0  to convert a jpg(first) via a program.When it displays on the lcd,it`s width is short.

what all configurations you used? in which order? more details will be helpful. What is the original size of the image which you try to display. when you use fb0 to display, its on which display? TV? which standard is set? please provide more details. 

The image is 320x240,my LCD is 320x240 too.

I set it in VID_ENC_OUTPUT_LCD1, VID_ENC_STD_320x240 mode .

I use Linux-2.6.18 kernel,there are some functions in davinci_platform.c I have used.

static void enableDigitalOutput(int bEnable)
 516 {
 517     if (bEnable) {
 518
 519         dispc_reg_out(VENC_VMOD, 0x2001);
 520         dispc_reg_out(VENC_CVBS, 0);
 521
 522         if (cpu_is_davinci_dm644x())
 523             davinci_writel(0, (DM644X_VPBE_REG_BASE + VPBE_PCR));
 524
 525         dispc_reg_out(VENC_LCDOUT, 0);///modified
 526
 527 //      dispc_reg_out(VENC_LCDOUT, 0x3);
 528
 529         dispc_reg_out(VENC_HSPLS, 0);
 530         dispc_reg_out(VENC_HSTART, 0);
 531         dispc_reg_out(VENC_HVALID, 0);
 532         dispc_reg_out(VENC_HINT, 0);
 533         dispc_reg_out(VENC_VSPLS, 0);
 534         dispc_reg_out(VENC_VSTART, 0);
 535         dispc_reg_out(VENC_VVALID, 0);
 536         dispc_reg_out(VENC_VINT, 0);
 537         dispc_reg_out(VENC_RGBCTL, 0);//
 538         dispc_reg_out(VENC_YCCCTL, 0);
 539         dispc_reg_out(VENC_DACSEL, 0);
 540
 541
 542         davinci_writel(0x5, DM365_VPBE_CLK_CTRL);//VPBE_CLK_CTRL modify by wangqin
 543
 544     }

893 static void davinci_enc_set_prgb(struct vid_enc_mode_info *mode_info)
 894 {
 895
 896     enableDigitalOutput(1);
 897
 898
 899     dispc_reg_out(VENC_VIDCTL, 0x01);
 900 //  dispc_reg_out(VENC_VIDCTL, 0x141);
 901     /* set VPSS clock */
 902     davinci_writel(0x18, SYS_VPSS_CLKCTL);
 903 //  davinci_writel(0x1a, SYS_VPSS_CLKCTL); //use EXTCLK;
 904     dispc_reg_out(VENC_DCLKCTL, 0x1);
 905     dispc_reg_out(VENC_DCLKPTN0,0x0);
  /* Set the OSD Divisor to 1. */
 911     dispc_reg_out(VENC_OSDCLK0, 0);
 912     dispc_reg_out(VENC_OSDCLK1, 1);
 913     /* Clear composite mode register */
 914     dispc_reg_out(VENC_CVBS, 0);
 915
 916     /* Set PINMUX1 to enable all outputs needed to support RGB666 */
 917     if (cpu_is_davinci_dm355()) {
 918         /* Enable the venc and dlcd clocks. */
 919         dispc_reg_out(VENC_CLKCTL, 0x11);
 920         davinci_cfg_reg(DM355_VOUT_FIELD_G70, PINMUX_RESV);
 921         davinci_cfg_reg(DM355_VOUT_COUTL_EN, PINMUX_RESV);
 922         davinci_cfg_reg(DM355_VOUT_COUTH_EN, PINMUX_RESV);
 923     } else if (cpu_is_davinci_dm365()) {
 924         /* DM365 pinmux */
 925         dispc_reg_out(VENC_CLKCTL, 0x11); //0x11
 926         davinci_cfg_reg(DM365_VOUT_FIELD_G81, PINMUX_RESV);
 927         davinci_cfg_reg(DM365_VOUT_COUTL_EN, PINMUX_RESV);
 928         davinci_cfg_reg(DM365_VOUT_COUTH_EN, PINMUX_RESV);
 929
 930         //////////////////////////////modified,colorbar
 931     //  u32 val=dispc_reg_in(VENC_VDPRO);
 932     //  dispc_reg_out(VENC_VDPRO,val|(1<<11));
 933         //////////////////////////////////////
 934     } else {
 935         dispc_reg_out(VENC_CMPNT, 0x100);
 936         if (cpu_is_davinci_dm644x()) {
 937             davinci_cfg_reg(DM644X_GPIO46_47, PINMUX_RESV);
 938             davinci_cfg_reg(DM644X_GPIO0, PINMUX_RESV);
 939             davinci_cfg_reg(DM644X_RGB666, PINMUX_RESV);
 940             davinci_cfg_reg(DM644X_LOEEN, PINMUX_RESV);
 941             davinci_cfg_reg(DM644X_GPIO3, PINMUX_RESV);
 942         } else {
 943             davinci_cfg_reg(DM357_GPIO46_47, PINMUX_RESV);
 944             davinci_cfg_reg(DM357_GPIO0, PINMUX_RESV);
 945             davinci_cfg_reg(DM357_RGB666, PINMUX_RESV);
 946             davinci_cfg_reg(DM357_LOEEN, PINMUX_RESV);
 947             davinci_cfg_reg(DM357_GPIO3, PINMUX_RESV);
 948         }
 949     }
 if (cpu_is_davinci_dm355()) {
 952         davinci_writel(mode_info->left_margin,
 953                    (DM355_OSD_REG_BASE + OSD_BASEPX));
 954         davinci_writel(mode_info->upper_margin,
 955                    (DM355_OSD_REG_BASE + OSD_BASEPY));
 956     } else if (cpu_is_davinci_dm365()) {
 957         davinci_writel(mode_info->left_margin,
 958                    (DM365_OSD_REG_BASE + OSD_BASEPX));
 959         davinci_writel(mode_info->upper_margin,
 960                    (DM365_OSD_REG_BASE + OSD_BASEPY));
 961     } else {
 962         davinci_writel(mode_info->left_margin,
 963                    (DM644X_OSD_REG_BASE + OSD_BASEPX));
 964         davinci_writel(mode_info->upper_margin,
 965                    (DM644X_OSD_REG_BASE + OSD_BASEPY));
 966     }
 967
 968     /* Set VIDCTL to select VCLKE = 1,
 969        VCLKZ =0, SYDIR = 0 (set o/p), DOMD = 0 */
 970     dispc_reg_merge(VENC_VIDCTL, 1 << VENC_VIDCTL_VCLKE_SHIFT,
 971             VENC_VIDCTL_VCLKE);
 972     dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_VCLKZ_SHIFT,
 973             VENC_VIDCTL_VCLKZ);
 974     dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_SYDIR_SHIFT,
 975             VENC_VIDCTL_SYDIR);
 976     dispc_reg_merge(VENC_VIDCTL, 0 << VENC_VIDCTL_YCDIR_SHIFT,
 977             VENC_VIDCTL_YCDIR);
 978
 979     dispc_reg_merge(VENC_DCLKCTL,
 980             1 << VENC_DCLKCTL_DCKEC_SHIFT, VENC_DCLKCTL_DCKEC);
 981
 982     dispc_reg_out(VENC_DCLKPTN0,0x1);
 983
 984
 985     davinci_enc_set_display_timing(mode_info);
 986     dispc_reg_out(VENC_SYNCCTL,
 987               (VENC_SYNCCTL_SYEV |
 988                VENC_SYNCCTL_SYEH|(1<<5)| VENC_SYNCCTL_HPL
 989                | VENC_SYNCCTL_VPL));
 990
 991     /* Configure VMOD. No change in VENC bit */
 992     dispc_reg_out(VENC_VMOD, 0x2011|(9<<1));
 993     dispc_reg_out(VENC_LCDOUT, 0x10);
}

I have modified logicpd_encoder.c ,It`s not affect,so I guess it related to the timing.

looks to me that following register programming needs to be verified.

 dispc_reg_out(VENC_OSDCLK0, 0);
 dispc_reg_out(VENC_OSDCLK1, 1);

looks like they need be programmed differently based on the timing. please refer to VPBE user guide.

In the above mail, its like this -

991     /* Configure VMOD. No change in VENC bit */

992     dispc_reg_out(VENC_VMOD, 0x2011|(9<<1));

can you check this?

Thanks for your kind reply.
I've solved the problem, our hardware have some fault.

 904     dispc_reg_out(VENC_DCLKCTL, 0x1);
This  code is wrong,the VENC_DCLKCTL should be 0.

I have some question about how to drive lcd.can u tell me your email?

mine okxuchen@163.com

Hi ,

Can you please share the details for displaying image on LCD.

I am only getting very small portion of display . I am assuimg there is some thing wrong with OSD settings , which i couldnt find ,

Any input is greatly appreciated.

Regards,

Dibin