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TDA4VM: Memory and cacheability

Clément Fau
Prodigy 135 points

Part Number: TDA4VM

Hi,

My goal is to compare the performance of the C66x and C71x cores. I use CCS and I followed the tutorial "CCS setup for J721E".
In order for the tests to be relevant, I try to make sure that the memory configurations are identical between the two cores, but also in some defined configurations.
To help me I use the SDK documentation, the C7x training, TDA4VM TRM, both corepac but I have some questions:

- I found in the SDK examples and in the C7x training, a lot of linker_map.cmd for the C7x with L2 6480 0000 as address. I guess this is the right address but I am unable to verify this information in any documentation, am I missing something or will future documentation come out?

- In order to configure the caches, I use csl_c7x.h and csl_cache.h provided by the SDK in the csl folder with the functions CSL_C7xSetL2CacheSize for the C7x and CACHE_setL1DSize for the C66x. I just found yesterday in this post e2e.ti.com/.../855158 that for the C7x, that the MMU needs to be enabled for this. It explains that the files to do this are in the TIDL package.Is the need to activate the MMU and the way to do it mentioned in a document that I would have missed?

- How to configure the cacheabilityof the MSMC for the C66x and C7x cores? In previous generations we configured the cacheabilityof the MSMC using MPAX registers and MAR for the C66x. I saw in the TRM that the MPAX registers are replaced by the RAT registers. Do you provide trainings for use?
For the C71x, the corepac mentions that the MMU replaces the MPAX and MAR. Do you have examples or trainings on this subject?


Thank you very much for your time,
Clément

  • 0
    Prodigy 135 points

    Hello,

    While working on the second question, I tried to initialize the MMU. I wanted to use the functions you recommended in the tidle folder of the PSDKRA, but I noticed that the CSL_c7xMMUInit function existed in the csl_c7x.h file in the folder <PSDKRA path>/pdk_jacinto/package/ti/csl/arch/c7x.

    I was already using this file for the CSL_c7xSetL2CacheSize function, and to compile, I had to include the associated library <PSDKRApath>/pdk_jacinto/package/ti/csl/lib/J721e/c7x/release/ti.csl.ae71

    But the call of the function CSL_c7xMMUInit raises 2 errors :

    unresolved symbol CSL_c7xSetTBR0, first referenced in C:/Users/User/Documents/psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/csl/lib/j721e/c7x/release/ti.csl.ae71<csl_c7x.oe71> and

    unresolved symbol CSL_c7xSetTCR0, first referenced in C:/Users/User/Documents/psdk_rtos_auto_j7_07_00_00_11/pdk_jacinto_07_00_00/packages/ti/csl/lib/j721e/c7x/release/ti.csl.ae71<csl_c7x.oe71>              

    I tried to find in the csl folder another library or a .c file, where these functions would be but I can't find it. I only found asm files in <PSDKRA path>/pdk_jacinto/package/ti/csl/arch/c7x/src.

    Thank you very much,

    Clément

  • 0 in reply to Clément Fau
    Prodigy 135 points

    Hello,

    I resolved my issue described in my second message. CSL_c7xSetTRBO and TCR0 are not defined in the csl_c7xecr.asm files in the src folder of csl.

    I found those definitions in the csl_c7xecr.asm in TIDL folder. But this files was containing other definitions that i did not want because already defined in the csl lib. So i just put an asm file in my project with the 2 definitions wanted.

    For the 3rd question in my post, the c7x training is providing pagetables file (c7x_simple_msmc_pte.c) generated by the memmap file. How do I generate mine? Is there any information about it somewhere?

    Still no answer for my first question.

    Thank you for your time,

    Clément

  • 0 in reply to Clément Fau
    TI__Genius 10365 points

    Clement,

    Apologize for a late reply. 

    For 1, I recommend that you contact our local TI FAE to get to access to C7x documents which we share via a system called CDDS. These documents should help provide memory map details for C7x. I believe even the TDA4x public TRM memory map should point to the same address as well.

    For 2. Yes the C7x training material is slightly outdated. Taking the required routines from TIDL is the right thing to do.

    For 3. The C7x training material was built on a fixed MMU page table using tools which require a DV environment to run. So there is no standalone tool which can be used to regenerate MMU as per different needs. However, our recommended approach is to link to BIOS and use the MMU setup mechanism provided by BIOS. By using BIOS you will get API's for MMU and even Cache API's so you will not require the CSL and/or some static MMU configuration. Again you can look at TIDL package, especially their standalone testbench for linking into BIOS.

    Regards,
    Shyam