J721EXSOMXEVM: superframe configuration

Hi max,

not sure how ub941 splits the frames. is it just alternate lines to each output? then i guess you just need to double the height, no change would be required in horizontal timings.

Rgds,

Brijesh

Hi Brijesh, The above diagram is from UB941 datasheet could you have a look of it to make sure that we are not missing anything. We want to use LEFT/RIGHT option as from application point of view it would be easy to manage. There are a couple of questions related to it (1) Do we need to do something special for DSI module as it will send stream to UB941? (2) UB941 wants to have double pixel clock. How can we configure DSS/DSI to have x2 pclk?

I got another question. How can I change number of lanes for DSI? Is it enough to change dsiPrms.numOfLanes to have 4 instead of 2?

Thanks

A team member of UB941 also recommending to change pclk. 

Thanks

Hi Brijesh, Please guide us how to meet the UB941 requirement of having double PCLK. I am okay to manipulate CTRLMMR directly if Sciclient_ API can't handle to proof that something is working. Moreover how can we change number of lanes and speed in DSI module? Currently it is dsiPrms.numOfLanes=2.

Thanks for the help.

Hi Brijesh, Did you get a chance to check how can we meet the pixel clock requirement of DS90UB941 for superframe configuration?

Thanks 

Hi max,

sorry what is the pixel clock requirement for 941? I did not get the question.

Regards,

Brijesh

Thanks for quick response.

We are looking to use DS90UB941 chip to drive two display panels by configuring it in the superframe configuration as shown in the following picture.

As per DS90UB941 datasheet, horizontal parameters of the video should be double alongwith pixel clock so that it can split image into two.

I am looking to find out how can increase the pixel clock on Jacinto7 platform to meet this requirement.

Thanks

Hi Max,

Could you please first try with the current pixel clock and half the current frame and see if it works fine?

Meanwhile i will try to figure out how to change pixel clock..

Regards,

Brijesh

Hi Brijesh,

Did you get a chance to check with team?

Please also let me know how can I change number of lanes and lane speed in DSI module?

Thanks

Hi max,

Not yet, but does the half frame configuration work fine?

Regards,

Brijesh

Hi, Actually we are seeing some issues with superframe configuration and not sure about the root cause so such information will be helpful.
Do you know how can we change number of lanes and lane speed in DSI module?

Thanks

Hi max,

There is an DSI parameter, numLanes. Please try changing it.

But please note we have tested only 2 lane output.

Regards,

Brijesh

Hi,
We are using dsiPrms.numOfLanes. 
What is about the lane speed?
Thanks

Hi max,

lane speed can be controlled in TBIT0 register. Please refer to the file ti-processor-sdk-rtos-j721e-evm-07_01_00_11\pdk_jacinto_07_01_00_45\packages\ti\drv\dss\src\drv\dctrl\dss_dctrlDsi.c, especially variable dphyTxRate. It is used to set lane speed.

Regards,

Brijesh