Hello,
There is 8MB (4 banks x 2MB) SRAM with ECC protection as part of Multicore Shared Memory Controller (MSMC). I'm interested about ECC protection of that SRAM memory.
My question is following: In order to monitor ECC for MSMC SRAM we need to check following RAM IDs inside CC_MSMC_WRAP_ECC_AGGR0:
- sram0_busecc
- sram1_busecc
- sram2_busecc
- sram3_busecc
I assume every RAM ID is related to one of the four memory banks? Is this correct? If not, please give me more details about this topic.
Best Regards,
Stefan.
