OMAP-L138: How way support a setup time of FSYNC using the McASP of DSP

Hi,

I believe you can satisfy the tSU(FSYNC FSYNC setup time) of >8ns by configuring the McASP transmitter/receiver for falling edge (CLKRP = CLKXP = 1). Relative to the BCLK, FS and DATA will appear to transition on the falling edge (>20ns before the rising edge, min PCM1840 BCLK period = 40ns). This satisfies the  >8ns setup and >8ns hold time.

Note: I include transmitter clock because the receiver has the option to operate synchronously from the ACLKX and AFSX signals.

According to the PCM1840 datasheet, the BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

2 x 25 ns = 50 ns: Max BCLK frequency = 20 MHz.

What is your desired sampling rate?

Another approach might be to delay the FS signal with logic on the PCB (RC delay or buffer), but this may need to be characterized across voltage and temperature for your application.

Hope this helps,
Mark