J721EXSOMXEVM: Ethernet Firmware unstable on power cycle

Hi Satish,

I will check and revert.

Regards

Vineet

Satish Lal Das2 said:

CpswPhy_enableState: PHY 0: falling back to manual mode

CpswPhy_enableState: PHY 0: new link caps: FD1000

CPSW has been stated sucesfully

This means that the PHY driver was originally requested to use autonegotiation, but BMSR[3] AUTONEG ABILITY is not set - so, by not detecting a auto-negotiation capability on the PHY side, it's falling back to manual mode. Please check if PHY's auto-negotiation is supported and if so, if BMSR[3] is the right bit to check if autonegotiation is supported.

Satish Lal Das2 said:

1 2 3 4 5 6

======================================================             CPSW Ethernet Firmware                      ====================================================== CPSW_9G Test on MAIN NAVSS Assertion @ Line: 1268 in src/cpsw_macport.c: version.ident_val == ipInfo->sgmiiInfo.versionInfo.moduleId : failed !!!

This is likely a clocking issue. The SGMII registers will be reset to zero if the SERDES clock is not initialized. That is the SERDES must be configured for the SGMII module to be configured.

Hi Misael,

Thank you for the reply.

On "BMSR[3] AUTONEG ABILITY" - From the BMSR register section of PHY DP83TG720 Datasheet, auto-negotiation ability is "Reserved".

I don't see any bit to be set here. 

#if defined(BUILD_MCU2_0)
static void CpswAppBoardUtils_configSerdesClks()
{
    uint32_t moduleId, clkId, clkRateHz;

    /* Below is port to SERDES mapping for CPSW9G
     * Port 1 – SERDES0 Lane 0 (Sierra – 2Lane – 16G capable)
     * Port 2 – SERDES0 Lane 1
     * Port 3 – SERDES1 Lane 0 (Sierra – 2Lane – 16G capable)
     * Port 4 – SERDES1 Lane 1
     * Port 5 – SERDES4 Lane 0 Torrent – 4Lane – 10G capable
     * Port 6 – SERDES4 Lane 1
     * Port 7 – SERDES4 Lane 2
     * Port 8 – SERDES4 Lane 3 */

    /* Configure the required PLLs for SERDES0 */
    moduleId  = TISCI_DEV_SERDES_16G0;
    clkId     = TISCI_DEV_SERDES_16G0_CORE_REF1_CLK;
    clkRateHz = 100000000;
    CpswAppUtils_clkRateSet(moduleId, clkId, clkRateHz);

    clkId     = TISCI_DEV_SERDES_16G0_CORE_REF_CLK;
    clkRateHz = 100000000;
    CpswAppUtils_clkRateSet(moduleId, clkId, clkRateHz);
    CpswAppUtils_setDeviceState(moduleId, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0U);

    /* Configure the required PLLs for SERDES1 */
    moduleId  = TISCI_DEV_SERDES_16G1;
    clkId     = TISCI_DEV_SERDES_16G1_CORE_REF1_CLK;
    clkRateHz = 100000000;
    CpswAppUtils_clkRateSet(moduleId, clkId, clkRateHz);

    clkId     = TISCI_DEV_SERDES_16G1_CORE_REF_CLK;
    clkRateHz = 100000000;
    CpswAppUtils_clkRateSet(moduleId, clkId, clkRateHz);
    CpswAppUtils_setDeviceState(moduleId, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0U);

    /* Configure the required PLLs for SERDES1 */
    moduleId  = TISCI_DEV_SERDES_10G0;
    clkId     = TISCI_DEV_SERDES_10G0_CORE_REF_CLK;
    clkRateHz = 100000000;
    CpswAppUtils_clkRateSet(moduleId, clkId, clkRateHz);
    CpswAppUtils_setDeviceState(moduleId, TISCI_MSG_VALUE_DEVICE_SW_STATE_ON, 0U);
}
#endif

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/**
 *  \file   board_cfg.c
 *
 *  \brief  EVM serdes configuration file
 *
 *  Configures the serdes module.
 *
 */

#include "board_serdes_cfg.h"

static Board_STATUS Board_CfgSgmii_0(void)
{
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane0EnableParams  = {0};

    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));

    /* SGMII Config */
    serdesLane0EnableParams.serdesInstance    = (CSL_SerdesInstance)SGMII_SERDES_INSTANCE0;
    serdesLane0EnableParams.baseAddr          = CSL_SERDES_16G0_BASE;
    serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;
    serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane0EnableParams.numLanes          = 0x2;
    serdesLane0EnableParams.laneMask          = 0x3;
    serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum    = SERDES_LANE_SELECT_CPSW;
    serdesLane0EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN3;

    serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;

    serdesLane0EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;

    CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);

    /* Select the IP type, IP instance num, Serdes Lane Number */
	// Lane 0 /* Added */
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLane0EnableParams.phyType,
                       serdesLane0EnableParams.phyInstanceNum,
                       serdesLane0EnableParams.serdesInstance,
                       SGMII_LANE_NUM0);
	// Lane 1
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLane0EnableParams.phyType,
                       serdesLane0EnableParams.phyInstanceNum,
                       serdesLane0EnableParams.serdesInstance,
                       SGMII_LANE_NUM1);


    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
                                 serdesLane0EnableParams.baseAddr,
                                 serdesLane0EnableParams.refClock,
                                 serdesLane0EnableParams.refClkSrc,
                                 serdesLane0EnableParams.serdesInstance,
                                 serdesLane0EnableParams.phyType);

    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }
    /* Assert PHY reset and disable all lanes */
    CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);

    /* Load the Serdes Config File */
    result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
    /* Return error if input params are invalid */
    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }

    /* Common Lane Enable API for lane enable, pll enable etc */
    laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
    if (laneRetVal != 0)
    {
        return BOARD_FAIL;
    }

    return BOARD_SOK;
}

static Board_STATUS Board_CfgSgmii_1(void) /* Addd for SGMII Support */
{
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane1EnableParams  = {0};

    memset(&serdesLane1EnableParams, 0, sizeof(serdesLane1EnableParams));

    /* SGMII Config */
    serdesLane1EnableParams.serdesInstance    = (CSL_SerdesInstance)SGMII_SERDES_INSTANCE1;
    serdesLane1EnableParams.baseAddr          = CSL_SERDES_16G1_BASE;
    serdesLane1EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    serdesLane1EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;
    serdesLane1EnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane1EnableParams.numLanes          = 0x2;
    serdesLane1EnableParams.laneMask          = 0x3;
    serdesLane1EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLane1EnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane1EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane1EnableParams.phyInstanceNum    = SERDES_LANE_SELECT_CPSW;
    serdesLane1EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN3;

    serdesLane1EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane1EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;

    serdesLane1EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane1EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;

    CSL_serdesPorReset(serdesLane1EnableParams.baseAddr);

    /* Select the IP type, IP instance num, Serdes Lane Number */
	// Lane 0
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLane1EnableParams.phyType,
                       serdesLane1EnableParams.phyInstanceNum,
                       serdesLane1EnableParams.serdesInstance,
                       SGMII_LANE_NUM0);
	// Lane 1
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
			   serdesLane1EnableParams.phyType,
			   serdesLane1EnableParams.phyInstanceNum,
			   serdesLane1EnableParams.serdesInstance,
			   SGMII_LANE_NUM1);				   


    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
                                 serdesLane1EnableParams.baseAddr,
                                 serdesLane1EnableParams.refClock,
                                 serdesLane1EnableParams.refClkSrc,
                                 serdesLane1EnableParams.serdesInstance,
                                 serdesLane1EnableParams.phyType);

    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }
    /* Assert PHY reset and disable all lanes */
    CSL_serdesDisablePllAndLanes(serdesLane1EnableParams.baseAddr, serdesLane1EnableParams.numLanes, serdesLane1EnableParams.laneMask);

    /* Load the Serdes Config File */
    result = CSL_serdesEthernetInit(&serdesLane1EnableParams);
    /* Return error if input params are invalid */
    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }

    /* Common Lane Enable API for lane enable, pll enable etc */
    laneRetVal = CSL_serdesLaneEnable(&serdesLane1EnableParams);
    if (laneRetVal != 0)
    {
        return BOARD_FAIL;
    }

    return BOARD_SOK;
}


static Board_STATUS Board_CfgSgmii_4(void) /* Addd for SGMII Support */
{
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane4EnableParams  = {0};

    memset(&serdesLane4EnableParams, 0, sizeof(serdesLane4EnableParams));

    /* SGMII Config */
    serdesLane4EnableParams.serdesInstance    = (CSL_SerdesInstance)SGMII_SERDES_INSTANCE4;
    serdesLane4EnableParams.baseAddr          = CSL_SERDES_16G1_BASE;
    serdesLane4EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    serdesLane4EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;
    serdesLane4EnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane4EnableParams.numLanes          = 0x2;
    serdesLane4EnableParams.laneMask          = 0x3;
    serdesLane4EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLane4EnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane4EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane4EnableParams.phyInstanceNum    = SERDES_LANE_SELECT_CPSW;
    serdesLane4EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN3;

    serdesLane4EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane4EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;

    serdesLane4EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane4EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;

    CSL_serdesPorReset(serdesLane4EnableParams.baseAddr);

    /* Select the IP type, IP instance num, Serdes Lane Number */
	// Lane 0
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLane4EnableParams.phyType,
                       serdesLane4EnableParams.phyInstanceNum,
                       serdesLane4EnableParams.serdesInstance,
                       SGMII_LANE_NUM0);
	// Lane 1
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
			   serdesLane4EnableParams.phyType,
			   serdesLane4EnableParams.phyInstanceNum,
			   serdesLane4EnableParams.serdesInstance,
			   SGMII_LANE_NUM1);

	// Lane 2
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
			   serdesLane4EnableParams.phyType,
			   serdesLane4EnableParams.phyInstanceNum,
			   serdesLane4EnableParams.serdesInstance,
			   SGMII_LANE_NUM2);

	// Lane 3
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
			   serdesLane4EnableParams.phyType,
			   serdesLane4EnableParams.phyInstanceNum,
			   serdesLane4EnableParams.serdesInstance,
			   SGMII_LANE_NUM3);				   


    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
                                 serdesLane4EnableParams.baseAddr,
                                 serdesLane4EnableParams.refClock,
                                 serdesLane4EnableParams.refClkSrc,
                                 serdesLane4EnableParams.serdesInstance,
                                 serdesLane4EnableParams.phyType);

    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }
    /* Assert PHY reset and disable all lanes */
    CSL_serdesDisablePllAndLanes(serdesLane4EnableParams.baseAddr, serdesLane4EnableParams.numLanes, serdesLane4EnableParams.laneMask);

    /* Load the Serdes Config File */
    result = CSL_serdesEthernetInit(&serdesLane4EnableParams);
    /* Return error if input params are invalid */
    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }

    /* Common Lane Enable API for lane enable, pll enable etc */
    laneRetVal = CSL_serdesLaneEnable(&serdesLane4EnableParams);
    if (laneRetVal != 0)
    {
        return BOARD_FAIL;
    }

    return BOARD_SOK;
}

static Board_STATUS Board_CfgQsgmii(void)
{
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane0EnableParams  = {0};

    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));

    /* QSGMII Config */
    serdesLane0EnableParams.serdesInstance    = (CSL_SerdesInstance)SGMII_SERDES_INSTANCE0;
    serdesLane0EnableParams.baseAddr          = CSL_SERDES_16G0_BASE;
    serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;
    serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_5G;
    serdesLane0EnableParams.numLanes          = 0x2;
    serdesLane0EnableParams.laneMask          = 0x3;
    serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_QSGMII;
    serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane0EnableParams.phyInstanceNum    = SERDES_LANE_SELECT_CPSW;
    serdesLane0EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN4;

    serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;

    serdesLane0EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane0EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;

    CSL_serdesPorReset(serdesLane0EnableParams.baseAddr);

    /* Select the IP type, IP instance num, Serdes Lane Number */
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLane0EnableParams.phyType,
                       serdesLane0EnableParams.phyInstanceNum,
                       serdesLane0EnableParams.serdesInstance,
                       SGMII_LANE_NUM1);


    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
                                 serdesLane0EnableParams.baseAddr,
                                 serdesLane0EnableParams.refClock,
                                 serdesLane0EnableParams.refClkSrc,
                                 serdesLane0EnableParams.serdesInstance,
                                 serdesLane0EnableParams.phyType);

    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }
    /* Assert PHY reset and disable all lanes */
    CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);

    /* Load the Serdes Config File */
    result = CSL_serdesEthernetInit(&serdesLane0EnableParams);
    /* Return error if input params are invalid */
    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }

    /* Common Lane Enable API for lane enable, pll enable etc */
    laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);
    if (laneRetVal != 0)
    {
        return BOARD_FAIL;
    }

    return BOARD_SOK;
}

/**
 *  \brief serdes configurations
 *
 *  The function configures the serdes1 module for one lane pcie interface
 *
 *  \return   BOARD_SOK in case of success or appropriate error code
 *
 */
Board_STATUS Board_serdesCfgSgmii(void)
{
    Board_STATUS ret;

    /* SERDES0 Initializations */
    //ret = Board_CfgSgmii();
	ret = Board_CfgSgmii_0();
    if(ret != BOARD_SOK)
    {
        return ret;
    }

	/* SERDES1 Initializations */ /* Added */
	ret = Board_CfgSgmii_1();
    if(ret != BOARD_SOK)
    {
        return ret;
    }

	/* SERDES4 Initializations */ /* Added */
	ret = Board_CfgSgmii_4();
    if(ret != BOARD_SOK)
    {
        return ret;
    }


    return BOARD_SOK;
}

/**
 *  \brief serdes configurations
 *
 *  The function configures the serdes1 module for one lane pcie interface
 *
 *  \return   BOARD_SOK in case of success or appropriate error code
 *
 */
Board_STATUS Board_serdesCfgQsgmii(void)
{
    Board_STATUS ret;

    /* SERDES0 Initializations */
    ret = Board_CfgQsgmii();
    if(ret != BOARD_SOK)
    {
        return ret;
    }

    return BOARD_SOK;
}

Hi Misael,

I checked with the Interface team and this PHY is a single-speed PHY , which means no auto negotiations. I guess that's why it is falling on Manual Mode. 

Could you please help us to fix the SerDes Clock issue which you mentioned in your reply, This is a blocker for us. Any help would be appreciated here.

Thanks,

Satish

For the PHY configuration that doesn't support auto-negotiation - when you open the port link via CPSW_IOCTL_OPEN_PORT_LINK ioctl, please pass the exact speed/duplexity (i.e. CPSW_SPEED_1GBIT, CPSW_DUPLEX_FULL). Passing _AUTO speed/duplex is used as an indication to try to use autonegotiation.

Which MAC port / SERDES are you having issues with? Let me check your changes and will get back to you.

Hi Misael,

Yes, We have set the fixed speed in PHY Driver. Here is the snippet of the code.

	
	/* Set Parameters for Automotive PHYs - Fixed Speed */
	cfg->isAutomotive = true;
	cfg->nwayCaps = CPSW_LINK_CAP_FD1000; // 1Gbit/s - Full Duplex
	

We are using SerDes 1 - Lane 0 for this testing.

We have six 720 PHY connected to the following SerDes Lanes. In the file, I sent I enabled all of these Lanes. For debugging & testing, we are enabling one PHY at a time.

SERDES1 Lane 0 
SERDES1 Lane 1
SERDES4 Lane 0 
SERDES4 Lane 1
SERDES4 Lane 2
SERDES4 Lane 3

Thanks,

Satish

cfg->nwayCaps is the mask of the auto-negotiation advertise values. What I meant is Cpsw_OpenPortLinkInArgs::linkConfig::speed and ::duplexity.

I see okay.. I will double-check.

This PHY driver is already tested & validated by one of the TI engineers by connecting a baseboard with J7 EVM. However, I will double-check (by adding some print statement)  to make sure Speed and Duplexity is matching with what you just mentioned here.

I am mainly facing an Integration issue. The engineer who tested this PHY used SerDes 0 -Lane 1 for testing. In our case, SerDes 0 Lane 0 & SerDes 0 Lane 1 is used for MAC-to-MAC connection, and the following SerDes Lanes are connected to 720 PHY's.

SERDES1 Lane 0 
SERDES1 Lane 1
SERDES4 Lane 0 
SERDES4 Lane 1
SERDES4 Lane 2
SERDES4 Lane 3

For the testing, I have just enabled SerDes 1 Lane 0 ( CPSW_MAC_PORT_2) in main_tirtos.c and that's where I started getting this error. 

======================================================
            CPSW Ethernet Firmware       
             
======================================================
CPSW_9G Test on MAIN NAVSS
Assertion @ Line: 1268 in src/cpsw_macport.c: version.ident_val == ipInfo->sgmiiInfo.versionInfo.moduleId : failed !!!

Hi Misa,

not sure if it helps but, there is something else you should -

I have Five J7 based custom boards, and only One board is sometimes (one out of several power cycles) is establishing the PHY Driver binding.  All of the boards are consistent with this error. So I wanted to focus on getting this issue fixed first before going to the Link issue. 

Hi Satish,

Please check the following points after you have hit that assert condition:

1. Read CTRLMMR_SERDES1_CLKSEL (0x00108410) and CTRLMMR_SERDES1_CLK1SEL (0x00108414). 

2. Read CTRLMMR_SERDES1_LN0_CTRL (0x00104090) - Value should be 0. 

3. Try enabling the only one lane in Board_CfgSgmii_1(), currently you are enabling both lanes.

4. Looking at the implementation of CSL_serdesIPSelect(), I think you need to pass laneNumber as 2 and 3 (instead of 0 and 1) for SERDES1. Please change the laneNumbers you are passing in Board_CfgSgmii_1() and see if behavior changes.

Hi Misael,

Thank you for sharing those memory locations. 

I passed that error now. The reason was, Clock for SerDes 1 was never initialized from "cpsw_appboardutils_j721e_evm.c". In my case clock inilization function (i.e. CpswAppBoardUtils_configSerdesClks();)  was called from void CpswAppBoardUtils_init(void)" but this function was never called. I moved "CpswAppBoardUtils_configSerdesClks()" & "Board_serdesCfgSgmii()" in "void CpswAppBoardUtils_initEthFw(void)" and now I don't see those error. 

Anyway here are the logs for that memory location - 

Before moving "CpswAppBoardUtils_configSerdesClks()" into "void CpswAppBoardUtils_initEthFw(void)" 

CTRLMMR_SERDES1_CLKSEL Value is      = 0x00000000
CTRLMMR_SERDES1_CLK1SEL Value is      = 0x00000000
CTRLMMR_SERDES1_LN0_CTRL Value is      = 0x00000000

After moving "CpswAppBoardUtils_configSerdesClks()" into "void CpswAppBoardUtils_initEthFw(void)" 

CTRLMMR_SERDES1_CLKSEL Value is      = 0x00000002
CTRLMMR_SERDES1_CLK1SEL Value is      = 0x00000002
CTRLMMR_SERDES1_LN0_CTRL Value is      = 0x00000000

The full log now is (Ignore Extra logs as I am using debug mode with Debug level 4) 

Enabling clocks for CPSW_9G!
=======================================================
            CPSW Ethernet Firmware                     
=======================================================
CPSW_9G Test on MAIN NAVSS
CTRLMMR_SERDES1_CLKSEL Value is      = 0x00000002
CTRLMMR_SERDES1_CLK1SEL Value is      = 0x00000002
CTRLMMR_SERDES1_LN0_CTRL Value is      = 0x00000000
CpswMacPort_configSgmii: MAC 2: Configuring SGMII in SGMII_WITH_PHY mode 
CpswPhy_setNextState: PHY 0: INIT -> FINDING (20 ticks)
CpswPhy_setNextState: PHY 0: FINDING -> FOUND (0 ticks)
CpswPhy_bindDriver: PHY 0: OUI:080028 Model:28 Ver:04 <-> 'vsc8514'
CpswPhy_bindDriver: PHY 0: OUI:080028 Model:28 Ver:04 <-> 'dp83822'
CpswPhy_bindDriver: PHY 0: OUI:080028 Model:28 Ver:04 <-> 'dp83867'
CpswPhy_bindDriver: PHY 0: OUI:080028 Model:28 Ver:04 <-> 'dp83tg720' : OK
CpswPhy_open: PHY 0: open
PHY 0 is alive
PHY 4 is alive
PHY 5 is alive
PHY 8 is alive
PHY 10 is alive
PHY 12 is alive

ETHFW Version   : 0.01.01
ETHFW Build Date: Feb 23, 2021
ETHFW Build Time: 23:47:10
ETHFW Commit SHA: 1dc91cd6

Dp83tg720_reset: PHY 0: global soft-reset
IPC_echo_test (core : mcu2_0) .....
CpswPhy_setNextState: PHY 0: FOUND -> RESET_WAIT (10 ticks)
Remote demo device (core : mcu2_0) .....
Dp83tg720_isResetComplete: PHY 0: global reset is  complete
CpswPhy_setNextState: PHY 0: RESET_WAIT -> ENABLE (0 ticks)
CpswPhy_enableState: PHY 0: enable
Dp83tg720_config: Applying configuration for Chip 4
Dp83tg720_readStraps: Strap is 0x2020
Dp83tg720_readStraps: Strap: Master Mode enabled
Dp83tg720_readStraps: Strap: SGMII Mode enabled
Dp83tg720_config: PHY 0: Enabling SGMII Mode
Dp83tg720_resetHw: PHY 0: global hard-reset
Dp83tg720_reset: PHY 0: global soft-reset
Dp83tg720_isResetComplete: PHY 0: global reset is  complete
SGMII_CTRL_1 value       = 0x027b
Dp83tg720_setLoopbackCfg: PHY 0: disable loopback
Dp83tg720_reset: PHY 0: global soft-reset
Dp83tg720_isResetComplete: PHY 0: global reset is  complete
Dp83tg720_configIntr: PHY 0: Disable interrupts
PHY 0: SGMII_CTRL       = 0x027b
PHY 0: RGMII_CTRL       = 0x0120
PHY 0: RGMII_DELAY_CTRL = 0x0000
PHY 0: RGMII_DELAY_TX_RX = 0x0980
PHY 0: REG_MasterSlave = 0xc001
CpswPhy_enableState: Automotive PHY detected. Skipping Auto-Negotiation
CpswPhy_enableState: PHY 0: req caps: FD1000 HD1000 FD100 HD100 FD10 HD10 
CpswPhy_enableState: PHY 0: PHY caps: FD1000 
CpswPhy_enableState: PHY 0: MAC caps: FD1000 FD100 HD100 FD10 HD10 
CpswPhy_enableState: PHY 0: refined caps: FD1000 
CpswPhy_enableState: PHY 0: PHY is notNWAY-capable
CpswPhy_enableState: PHY 0: falling back to manual mode
CpswPhy_enableState: PHY 0: new link caps: FD1000 
CpswPhy_enableState: PHY 0: manual setup
CpswPhy_setupManual: PHY 0: requested mode: 1 Gbps full-duplex
CpswPhy_setNextState: PHY 0: ENABLE -> LINK_WAIT (50 ticks)
Host MAC address: 70:ff:76:1d:92:c2
Host MAC address: 70:ff:76:1d:92:c2
[NIMU_NDK] CPSW has been started successfully

CPSW NIMU application, IP address I/F 1: 192.168.1.203

Rx Flow for Software Inter-VLAN Routing is up

SerDes Lanes is still a mystery to me. I changed the Lane number to 2 & 3 (instead of 0 & 1) and enabled only lane 2 in CSL_serdesIPSelect() for SerDes 1. However, I revert the Lane number from 2 & 3 to 0 & 1 and tested with only Lane 0.

The result was - No matter what lane number I keep i.e.  0 or 2 I still get the same logs. I would have expected one of them not to work. Not sure what I am missing here but do you agree that one of those tests should fail?

I am using SDK 7.0 , could you please let me know what Lane number I should use for Following SerDes Instance  -

SERDES0 Lane 0  - ?
SERDES0 Lane 1  - ?
SERDES1 Lane 0 - ?
SERDES1 Lane 1 - ?
SERDES4 Lane 0 - ?
SERDES4 Lane 1 - ?
SERDES4 Lane 2 - ?
SERDES4 Lane 3  - ?

Thank you again for your help.

Thanks,

Satish

Hi Misael,

Yes looking at the logs (last line i.e.LINK_WAIT -> LINKED (0 ticks)) Linked is established between my J7 board and my media converter board. Since I don't have a virtual MAC port in A72 core I can't really ping partner computer from J7. 

CpswPhy_setNextState: PHY 0: LINK_WAIT -> FOUND (0 ticks)
Dp83tg720_reset: PHY 0: global soft-reset
CpswPhy_setNextState: PHY 0: FOUND -> RESET_WAIT (10 ticks)
Dp83tg720_isResetComplete: PHY 0: global reset is  complete
CpswPhy_setNextState: PHY 0: RESET_WAIT -> ENABLE (0 ticks)
CpswPhy_enableState: PHY 0: enable
Dp83tg720_config: Applying configuration for Chip 4
Dp83tg720_readStraps: Strap is 0x2020
Dp83tg720_readStraps: Strap: Master Mode enabled
Dp83tg720_readStraps: Strap: SGMII Mode enabled
Dp83tg720_config: PHY 0: Enabling SGMII Mode
Dp83tg720_resetHw: PHY 0: global hard-reset
Dp83tg720_reset: PHY 0: global soft-reset
Dp83tg720_isResetComplete: PHY 0: global reset is  complete
SGMII_CTRL_1 value       = 0x027b
Dp83tg720_setLoopbackCfg: PHY 0: disable loopback
Dp83tg720_reset: PHY 0: global soft-reset
Dp83tg720_isResetComplete: PHY 0: global reset is  complete
Dp83tg720_configIntr: PHY 0: Disable interrupts
PHY 0: SGMII_CTRL       = 0x027b
PHY 0: RGMII_CTRL       = 0x0120
PHY 0: RGMII_DELAY_CTRL = 0x0000
PHY 0: RGMII_DELAY_TX_RX = 0x0980
PHY 0: REG_MasterSlave = 0xc001
CpswPhy_enableState: Automotive PHY detected. Skipping Auto-Negotiation
CpswPhy_enableState: PHY 0: req caps: FD1000 HD1000 FD100 HD100 FD10 HD10 
CpswPhy_enableState: PHY 0: PHY caps: FD1000 
CpswPhy_enableState: PHY 0: MAC caps: FD1000 FD100 HD100 FD10 HD10 
CpswPhy_enableState: PHY 0: refined caps: FD1000 
CpswPhy_enableState: PHY 0: PHY is notNWAY-capable
CpswPhy_enableState: PHY 0: falling back to manual mode
CpswPhy_enableState: PHY 0: new link caps: FD1000 
CpswPhy_enableState: PHY 0: manual setup
CpswPhy_setupManual: PHY 0: requested mode: 1 Gbps full-duplex
CpswPhy_setNextState: PHY 0: ENABLE -> LINK_WAIT (50 ticks)
CpswPhy_setNextState: PHY 0: LINK_WAIT -> LINKED (0 ticks)

I connected my computer to the RJ45 connector and tried to ping the host port i.e. 192.168.1.203 but It told me "Host is unreachable". Do you think I can ping the Host port without having virtual MAC port on A72 core?

Thanks,

Satish

Hi Misa,

Since the SerDes Clock issue is resolved. I think we can close this E2E thread.

Thanks,

Satish

Hi Misa,

Opening this thread again. I started testing each PHY one by one by assigning the Lane number as suggested. These are the Lanes mapped to 720 PHY. I can see that the first two Lane works. However, Lanes from SerDes4 is not working. I don't even see any logs. 

• SERDES1 Lane 0 - serdesInstance=CSL_SIERRA_SERDES1, serdeslaneNum=2               - WORKS
• SERDES1 Lane 1 - serdesInstance=CSL_SIERRA_SERDES1, serdeslaneNum=3               - WORKS
• SERDES4 Lane 0 - serdesInstance=CSL_TORRENT_SERDES0, serdeslaneNum=0           - DOESN'T WORK
• SERDES4 Lane 1 - serdesInstance=CSL_TORRENT_SERDES0, serdeslaneNum=1           - NOT TESTED
• SERDES4 Lane 2 - serdesInstance=CSL_TORRENT_SERDES0, serdeslaneNum=2           - NOT TESTED
• SERDES4 Lane 3  - serdesInstance=CSL_TORRENT_SERDES0, serdeslaneNum=3          - NOT TESTED

I don't see any logs from ethernet firmware when Enable SerDes4 Lane 0. These are the changes I made. 

main_tirtos.c

static EthFw_Port gEthAppPorts[] =
{
    {
        .portNum    = CPSW_MAC_PORT_4, /* RGMII */
        .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
    },
#if 0
    {
        .portNum    = CPSW_MAC_PORT_0,
        .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U },
    },
    {
        .portNum    = CPSW_MAC_PORT_1, /* QSGMII main */
        .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
    },
    {
        .portNum    = CPSW_MAC_PORT_3, /* RGMII */
        .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
    },
    {
        .portNum    = CPSW_MAC_PORT_7, /* RGMII */
        .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
    },

    {
        .portNum    = CPSW_MAC_PORT_4, /* QSGMII sub */
        .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
    },
    {
        .portNum    = CPSW_MAC_PORT_5, /* QSGMII sub */
        .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
    },
    {
        .portNum    = CPSW_MAC_PORT_6, /* QSGMII sub */
        .vlanConfig = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
    },
#endif
};

board_serdes_cfg.c 

#define SGMII_SERDES_INSTANCE4      (CSL_TORRENT_SERDES0)

static Board_STATUS Board_CfgSgmii_4(void) /* Addd for SGMII Support */
{
    CSL_SerdesResult result;
    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;
    CSL_SerdesLaneEnableParams serdesLane4EnableParams  = {0};

    memset(&serdesLane4EnableParams, 0, sizeof(serdesLane4EnableParams));

    /* SGMII Config */
    serdesLane4EnableParams.serdesInstance    = (CSL_SerdesInstance)SGMII_SERDES_INSTANCE4;
    serdesLane4EnableParams.baseAddr          = CSL_SERDES_16G1_BASE;
    serdesLane4EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;
    serdesLane4EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;
    serdesLane4EnableParams.linkRate          = CSL_SERDES_LINK_RATE_1p25G;
    serdesLane4EnableParams.numLanes          = 0x2;
    serdesLane4EnableParams.laneMask          = 0x3;
    serdesLane4EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;
    serdesLane4EnableParams.phyType           = CSL_SERDES_PHY_TYPE_SGMII;
    serdesLane4EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;
    serdesLane4EnableParams.phyInstanceNum    = SERDES_LANE_SELECT_CPSW;
    serdesLane4EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN3;

    serdesLane4EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane4EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;

    serdesLane4EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;
    serdesLane4EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;

    CSL_serdesPorReset(serdesLane4EnableParams.baseAddr);

    /* Select the IP type, IP instance num, Serdes Lane Number */
	// Lane 0
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLane4EnableParams.phyType,
                       serdesLane4EnableParams.phyInstanceNum,
                       serdesLane4EnableParams.serdesInstance,
                       SGMII_LANE_NUM0);
#if 0
	// Lane 1
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
			   serdesLane4EnableParams.phyType,
			   serdesLane4EnableParams.phyInstanceNum,
			   serdesLane4EnableParams.serdesInstance,
			   SGMII_LANE_NUM1);

	// Lane 2
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
			   serdesLane4EnableParams.phyType,
			   serdesLane4EnableParams.phyInstanceNum,
			   serdesLane4EnableParams.serdesInstance,
			   SGMII_LANE_NUM2);

	// Lane 3
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
			   serdesLane4EnableParams.phyType,
			   serdesLane4EnableParams.phyInstanceNum,
			   serdesLane4EnableParams.serdesInstance,
			   SGMII_LANE_NUM3);				   
#endif

    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,
                                 serdesLane4EnableParams.baseAddr,
                                 serdesLane4EnableParams.refClock,
                                 serdesLane4EnableParams.refClkSrc,
                                 serdesLane4EnableParams.serdesInstance,
                                 serdesLane4EnableParams.phyType);

    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }
    /* Assert PHY reset and disable all lanes */
    CSL_serdesDisablePllAndLanes(serdesLane4EnableParams.baseAddr, serdesLane4EnableParams.numLanes, serdesLane4EnableParams.laneMask);

    /* Load the Serdes Config File */
    result = CSL_serdesEthernetInit(&serdesLane4EnableParams);
    /* Return error if input params are invalid */
    if (result != CSL_SERDES_NO_ERR)
    {
        return BOARD_FAIL;
    }

    /* Common Lane Enable API for lane enable, pll enable etc */
    laneRetVal = CSL_serdesLaneEnable(&serdesLane4EnableParams);
    if (laneRetVal != 0)
    {
        return BOARD_FAIL;
    }

    return BOARD_SOK;
}

As soon as I enable SerDes 4 I don't see any logs from Ethernet firmware. Any suggestion would be helpful.

Thanks,

Satish

serdesLane4EnableParams.baseAddr          = CSL_SERDES_16G1_BASE;"

Does this looks correct to you for SerDes Instance 4? In some places in code, I found it should be 10G0 ?

Hi Misa,

I changed "serdesLane4EnableParams.baseAddr          = CSL_SERDES_16G1_BASE;"" to  serdesLane4EnableParams.baseAddr          = CSL_SERDES_10G0_BASE;" for SerDes4 and it let me progress to validate next two Lanes in SerDes4. Now the result looks like below -

• SERDES1 Lane 0 - serdesInstance=CSL_SIERRA_SERDES1, serdeslaneNum=2               - WORKS
• SERDES1 Lane 1 - serdesInstance=CSL_SIERRA_SERDES1, serdeslaneNum=3               - WORKS
• SERDES4 Lane 0 - serdesInstance=CSL_TORRENT_SERDES0, serdeslaneNum=0           - WORKS
• SERDES4 Lane 1 - serdesInstance=CSL_TORRENT_SERDES0, serdeslaneNum=1           - WORKS
• SERDES4 Lane 2 - serdesInstance=CSL_TORRENT_SERDES0, serdeslaneNum=2           - DOESN'T WORK
• SERDES4 Lane 3  - serdesInstance=CSL_TORRENT_SERDES0, serdeslaneNum=3          - NOT TESTED

And the error I get is  -

Enabling clocks for CPSW_9G!
=======================================================
            CPSW Ethernet Firmware                     
=======================================================
CPSW_9G Test on MAIN NAVSS
CTRLMMR_SERDES1_CLKSEL Value is      = 0x00000002
CTRLMMR_SERDES1_CLK1SEL Value is      = 0x00000002
CTRLMMR_SERDES1_LN0_CTRL Value is      = 0x00000000
Assertion @ Line: 1278 in src/cpsw_macport.c: version.ident_val == ipInfo->sgmiiInfo.versionInfo.moduleId : failed !!!

This seems same error as before. 

I noticed that only two lanes of SerDes4 is working and started inspecting the flags. Does these setting could restrict to use only two lanes? 

serdesLane4EnableParams.numLanes = 0x2;
serdesLane4EnableParams.laneMask = 0x3;

If So, What changes I need to enable all 4 lenses of SerDes4?

Thanks,

Satish

Satish,

Correct, CSL_SERDES_10G0_BASE is the baseaddress for CSL_TORRENT_SERDES0.

Try with numLanes = 4 and laneMask = 0xF.

Also try having all CSL_serdesIPSelect() calls for all 4 lanes regardless of the port you have enabled in gEthAppPorts.

	// Lane 0
    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
                       serdesLane4EnableParams.phyType,
                       serdesLane4EnableParams.phyInstanceNum,
                       serdesLane4EnableParams.serdesInstance,
                       SGMII_LANE_NUM0);
#if 0 <- Change this to "#if 1"
	// Lane 1
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
			   serdesLane4EnableParams.phyType,
			   serdesLane4EnableParams.phyInstanceNum,
			   serdesLane4EnableParams.serdesInstance,
			   SGMII_LANE_NUM1);

	// Lane 2
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
			   serdesLane4EnableParams.phyType,
			   serdesLane4EnableParams.phyInstanceNum,
			   serdesLane4EnableParams.serdesInstance,
			   SGMII_LANE_NUM2);

	// Lane 3
	CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,
			   serdesLane4EnableParams.phyType,
			   serdesLane4EnableParams.phyInstanceNum,
			   serdesLane4EnableParams.serdesInstance,
			   SGMII_LANE_NUM3);				   
#endif

Regards,

-Misa

Hi Misa

Using numLanes = 4 and laneMask = 0xF. , I passed that error now.  However, there is something weird is happening.

Usually when PHY-Driver bind happns I noticed 'OK" message in front of "dp83tg720". In this case "OK" message is coming from a "generic" driver. and then 

several "GenericPhy_isResetComplete: PHY 10: reset is notcomplete" messages.

CpswPhy_bindDriver: PHY 10: OUI:367e36 Model:1f Ver:08 <-> 'dp83tg720'
CpswPhy_bindDriver: PHY 10: OUI:367e36 Model:1f Ver:08 <-> 'generic' : OK

Do you know what could be the issue here?

Here is Full log.

Enabling clocks for CPSW_9G!
=======================================================
            CPSW Ethernet Firmware                     
=======================================================
CPSW_9G Test on MAIN NAVSS
CTRLMMR_SERDES1_CLKSEL Value is      = 0x00000002
CTRLMMR_SERDES1_CLK1SEL Value is      = 0x00000002
CTRLMMR_SERDES1_LN0_CTRL Value is      = 0x00000000
CpswMacPort_configSgmii: MAC 6: Configuring SGMII in SGMII_WITH_PHY mode 
CpswPhy_setNextState: PHY 10: INIT -> FINDING (20 ticks)
CpswPhy_setNextState: PHY 10: FINDING -> FOUND (0 ticks)
CpswPhy_bindDriver: PHY 10: OUI:367e36 Model:1f Ver:08 <-> 'vsc8514'
CpswPhy_bindDriver: PHY 10: OUI:367e36 Model:1f Ver:08 <-> 'dp83822'
CpswPhy_bindDriver: PHY 10: OUI:367e36 Model:1f Ver:08 <-> 'dp83867'
CpswPhy_bindDriver: PHY 10: OUI:367e36 Model:1f Ver:08 <-> 'dp83tg720'
CpswPhy_bindDriver: PHY 10: OUI:367e36 Model:1f Ver:08 <-> 'generic' : OK
CpswPhy_open: PHY 10: open
PHY 0 is alive
PHY 4 is alive
PHY 5 is alive
PHY 8 is alive
PHY 10 is alive
PHY 12 is alive

ETHFW Version   : 0.01.01
ETHFW Build Date: Feb 23, 2021
ETHFW Build Time: 23:47:10
ETHFW Commit SHA: 1dc91cd6

GenericPhy_reset: PHY 10: reset
IPC_echo_test (core : mcu2_0) .....
CpswPhy_setNextState: PHY 10: FOUND -> RESET_WAIT (10 ticks)
Remote demo device (core : mcu2_0) .....
GenericPhy_isResetComplete: PHY 10: reset is notcomplete
GenericPhy_isResetComplete: PHY 10: reset is notcomplete
GenericPhy_isResetComplete: PHY 10: reset is notcomplete
Host MAC address: 70:ff:76:1d:92:c2
GenericPhy_isResetComplete: PHY 10: reset is notcomplete
Host MAC address: 70:ff:76:1d:92:c2
GenericPhy_isResetComplete: PHY 10: reset is notcomplete
[NIMU_NDK] CPSW has been started successfully
GenericPhy_isResetComplete: PHY 10: reset is notcomplete

CPSW NIMU application, IP address I/F 1: 192.168.1.203

GenericPhy_isResetComplete: PHY 10: reset is notcomplete
GenericPhy_isResetComplete: PHY 10: reset is notcomplete
Rx Flow for Software Inter-VLAN Routing is up
GenericPhy_isResetComplete: PHY 10: reset is notcomplete
GenericPhy_isResetComplete: PHY 10: reset is notcomplete
GenericPhy_isResetComplete: PHY 10: reset is notcomplete

Thanks,

Satish

I am seeing the Same error with Last Port, i.e. SerDes 4 Lane 3, where PHY- Driver bind happens for the generic driver. 

Satish,

PHY device-to-driver binding is done based on IDR1 and IDR2 registers. From the logs, I see that the driver read: OUI:367e36 Model:1f, but your dp83tg720 driver doesn't seem to have support for it.

Check in your dp83tg720's isPhyDevSupported() function is this particular OUI/Model numbers are supported.

The 'generic' PHY driver is a fallback option and it's expected to see functional errors if the PHY requires configuration beyond IEEE standard registers.

Hi Misa,

Yes, You are right. The "isPhyDevSupported()" function has support for following two OUI/Model.

#define DP83TG720_OUI (0x080028U)
#define DP83TG720_MODEL (0x28U)

Here is the function from Driver.

static bool Dp83tg720_isPhyDevSupported(CpswPhy_Handle hPhy,
                                      const CpswPhy_Version *version)
{
    bool supported = false;
    if ((version->oui == DP83TG720_OUI) &&
        (version->model == DP83TG720_MODEL))
    {
        supported = true;
    }
	
	//Determine phy version
	if (version->revision == DP83TG720ES1_PHY_ID)
		dp83tg720.chip = DP83720_ES1;
    else if (version->revision == DP83TG720ES2_PHY_ID)
		dp83tg720.chip = DP83720_ES2;
    else if (version->revision == DP83TG720CS1_PHY_ID)
		dp83tg720.chip = DP83720_CS1;
    else if (version->revision == DP83TG720CS2_PHY_ID)
		dp83tg720.chip = DP83720_CS2;

    return supported;
}

Total we have 6 of these PHY's and all are the same parts, what could be the reason for different OUI/Model number, and also It is not functioning as other parts?

Anyway I have added the this new OUI & Model in "isPhyDevSupported()" function and looks like PHY is binding with correct driver. However It is stuck with "gobal reset is not complete". 

Enabling clocks for CPSW_9G!
=======================================================
            CPSW Ethernet Firmware                     
=======================================================
CPSW_9G Test on MAIN NAVSS
CTRLMMR_SERDES1_CLKSEL Value is      = 0x00000002
CTRLMMR_SERDES1_CLK1SEL Value is      = 0x00000002
CTRLMMR_SERDES1_LN0_CTRL Value is      = 0x00000000
CpswMacPort_configSgmii: MAC 6: Configuring SGMII in SGMII_WITH_PHY mode 
CpswPhy_setNextState: PHY 10: INIT -> FINDING (20 ticks)
CpswPhy_setNextState: PHY 10: FINDING -> FOUND (0 ticks)
CpswPhy_bindDriver: PHY 10: OUI:327e32 Model:1f Ver:08 <-> 'vsc8514'
CpswPhy_bindDriver: PHY 10: OUI:327e32 Model:1f Ver:08 <-> 'dp83822'
CpswPhy_bindDriver: PHY 10: OUI:327e32 Model:1f Ver:08 <-> 'dp83867'
CpswPhy_bindDriver: PHY 10: OUI:327e32 Model:1f Ver:08 <-> 'dp83tg720' : OK
CpswPhy_open: PHY 10: open
PHY 0 is alive
PHY 4 is alive
PHY 5 is alive
PHY 8 is alive
PHY 10 is alive
PHY 12 is alive

ETHFW Version   : 0.01.01
ETHFW Build Date: Feb 23, 2021
ETHFW Build Time: 23:47:10
ETHFW Commit SHA: 1dc91cd6

Dp83tg720_reset: PHY 10: global soft-reset
IPC_echo_test (core : mcu2_0) .....
CpswPhy_setNextState: PHY 10: FOUND -> RESET_WAIT (10 ticks)
Remote demo device (core : mcu2_0) .....
Dp83tg720_isResetComplete: PHY 10: global reset is not complete
Dp83tg720_isResetComplete: PHY 10: global reset is not complete
Dp83tg720_isResetComplete: PHY 10: global reset is not complete
Dp83tg720_isResetComplete: PHY 10: global reset is not complete

Thanks,

Satish

There is something else I am noticing -

Sometimes during power cycle OUI numbers are changing. For example for MAC 6, I saw this text - 

CpswPhy_bindDriver: PHY 10: OUI:367e36 Model:1f Ver:08 <-> 'generic' : OK

Next power cycle I saw.

CpswPhy_bindDriver: PHY 10: OUI:327e32 Model:1f Ver:08 <-> 'dp83tg720' : OK

No change in code, Just power cycle the board. Is this something we should expect? I thought OUI number is unique.

Huh - this is not normal. I'd suggest checking your board hardware.

I was just having a look at the OUI values and they seem invalid ones (i.e. don't belong to any manufacturer).

If the PHY IDR1/IDR2 register reads were not successful (hence the invalid OUI value), I don't think we can be sure about any register read/write done on that PHY.

First step would be to be able to get valid OUI, same as other PHYs. If possible try with another board.

Hey Misa,

On the other board too. I am seeing the same behavior - 

In One power cycle, I saw - 

Enabling clocks for CPSW_9G!
=======================================================
            CPSW Ethernet Firmware                     
=======================================================
CPSW_9G Test on MAIN NAVSS
CTRLMMR_SERDES1_CLKSEL Value is      = 0x00000002
CTRLMMR_SERDES1_CLK1SEL Value is      = 0x00000002
CTRLMMR_SERDES1_LN0_CTRL Value is      = 0x00000000
CpswMacPort_configSgmii: MAC 6: Configuring SGMII in SGMII_WITH_PHY mode 
CpswPhy_setNextState: PHY 10: INIT -> FINDING (20 ticks)
CpswPhy_setNextState: PHY 10: FINDING -> FOUND (0 ticks)
CpswPhy_bindDriver: PHY 10: OUI:103dd0 Model:0f Ver:07 <-> 'vsc8514'
CpswPhy_bindDriver: PHY 10: OUI:103dd0 Model:0f Ver:07 <-> 'dp83822'
CpswPhy_bindDriver: PHY 10: OUI:103dd0 Model:0f Ver:07 <-> 'dp83867'
CpswPhy_bindDriver: PHY 10: OUI:103dd0 Model:0f Ver:07 <-> 'dp83tg720'
CpswPhy_bindDriver: PHY 10: OUI:103dd0 Model:0f Ver:07 <-> 'generic' : OK

Second Power Cycle

Enabling clocks for CPSW_9G!
=======================================================
            CPSW Ethernet Firmware                     
=======================================================
CPSW_9G Test on MAIN NAVSS
CTRLMMR_SERDES1_CLKSEL Value is      = 0x00000002
CTRLMMR_SERDES1_CLK1SEL Value is      = 0x00000002
CTRLMMR_SERDES1_LN0_CTRL Value is      = 0x00000000
CpswMacPort_configSgmii: MAC 6: Configuring SGMII in SGMII_WITH_PHY mode 
CpswPhy_setNextState: PHY 10: INIT -> FINDING (20 ticks)
CpswPhy_setNextState: PHY 10: FINDING -> FOUND (0 ticks)
CpswPhy_bindDriver: PHY 10: OUI:080028 Model:28 Ver:04 <-> 'vsc8514'
CpswPhy_bindDriver: PHY 10: OUI:080028 Model:28 Ver:04 <-> 'dp83822'
CpswPhy_bindDriver: PHY 10: OUI:080028 Model:28 Ver:04 <-> 'dp83867'
CpswPhy_bindDriver: PHY 10: OUI:080028 Model:28 Ver:04 <-> 'dp83tg720' : OK

This looks the same as the other 4 PHY's.

Third power cycle 

Enabling clocks for CPSW_9G!
=======================================================
            CPSW Ethernet Firmware                     
=======================================================
CPSW_9G Test on MAIN NAVSS
CTRLMMR_SERDES1_CLKSEL Value is      = 0x00000002
CTRLMMR_SERDES1_CLK1SEL Value is      = 0x00000002
CTRLMMR_SERDES1_LN0_CTRL Value is      = 0x00000000
CpswMacPort_configSgmii: MAC 6: Configuring SGMII in SGMII_WITH_PHY mode 
CpswPhy_setNextState: PHY 10: INIT -> FINDING (20 ticks)
CpswPhy_setNextState: PHY 10: FINDING -> FOUND (0 ticks)
CpswPhy_bindDriver: PHY 10: OUI:103dd0 Model:0f Ver:07 <-> 'vsc8514'
CpswPhy_bindDriver: PHY 10: OUI:103dd0 Model:0f Ver:07 <-> 'dp83822'
CpswPhy_bindDriver: PHY 10: OUI:103dd0 Model:0f Ver:07 <-> 'dp83867'
CpswPhy_bindDriver: PHY 10: OUI:103dd0 Model:0f Ver:07 <-> 'dp83tg720'
CpswPhy_bindDriver: PHY 10: OUI:103dd0 Model:0f Ver:07 <-> 'generic' : OK

Hi Satish,

Following up after long time. Is this issue still open ?

Regards

Vineet