OMAP 3730 SPI efficiency

I don't see what else you can do but put your bus width to 32 bits and choose the highest bitrate available. The SPI bus is not designed to exchange big chunks of data, maybe using the McBSP between both OMAPs would get you better results.

Dean

The McSPI interface can be used but as you have already pointed out there is some overhead for the toggling of the CS pin between words. As you also noted this can be minimized by using the force mode.  Something else to consider is that the McSPI FIFO is only 64 bytes which is only 16 32bit  words. The full FIFO can be dedicated to TX or RX but shared  if used for both.

As the support team mentioned, another option is using a McBSP. The McBSP and McSPI support the same maximum bit speed but the McBSP can sustain this 100% as there are no pauses for sync pulses. The McBSP also has a FIFO of 128 32bit words (McBSP2 has an additional 1024 word FIFO) which will reduce the processor overhead or reduce the DMA frequency. The McSPI and McBSP 2-5 only support synchronous transmit and receive channles but McBSP1 can be used in 6-pin mode to support true asynchronous transmit and receive channels.

  Paul

Let me make sure I understand.  One OMAP is a master-transmitter and the other is a master-receiver.

• So is the master configured as "transmit only" and the slave as "receive only", or are both setup as "transmit/receive"?  This has implications on the FIFO size as well as some of the options available.
• Are any other channels enabled for the SPI, or is this the only channel in use?  That is, are other chip enables in use?
• Related to the last question, how have you programmed the bits MCSPI_MODULCTRL[SINGLE]?
• For each processor, are you using interrupts or DMA to service the SPI?
• A couple register dumps might be the best way to answer all these questions.

Dean Harken said:

On a related note I don't see where in the TRM the time between word transmissions (normal mode or force spim_csx mode) is specified or controlled.

If it's there, I can't find it either.  Whatever it is, it's not programmable as far as I can tell.  Do you have a scope hooked up to your board?  If so, how much time (e.g. in spi_clk cycles) does it stay de-asserted between cycles? 

Dean Harken said:

What about the "force spim_csx mode"?   This mode causes chip select to remain asserted between bus cycles but does this significantly reduce the time between transmission cycles?

 I don't know about significantly but yes, I do expect that it will reduce the time between transmission cycles.  At a minimum it should buy you a couple cycles related to the time delay for chip select to go low at the start and go high at the end.  It might buy you more depending on how long chip select stays high between successive transfers.

Actually, one OMAP is a master transmitter/receiver and the other is a slave transmitter/receiver.  That is, I expect the master to be the only one who will initiate bus transactions.

On the OMAP that is the master, there will be multiple channels in use.  For the slave, there is only one.

We are still in the design stage so no code has been written yet, so I can't provide a register dump.  I am planning on using DMA and the FIFO for servicing the SPI.

OK.  Thanks.  This is the kind of information that I am looking for.

PS.  Lots of good info including code examples are available in this thread:

OMAP3 McSPI Turbo Mode Example?