TDA4VM: Data acquisition from UB940

Mohamed SASSI

Part Number: TDA4VM
Other Parts Discussed in Thread: USB2ANY, ALP

Hello experts,

I am trying to build an application around the TDA4VM EVM and the UB940. The idea is to get data (videos or images) from UB940 through the CSI2 interface and then display it in a screen using one of the interfaces (HDMI, OLDI or RGB). Is there any examples I can use in the PDK with the no-boot mode or I should boot from SD card and use the SDK.

Thank you in advance.

Best Regards,
Mohamed

over 3 years ago

0 Mayank Mangla over 3 years ago

TI__Mastermind 24525 points

Hello Mohamed,

There are example using UB960. You may modify sensor driver source to configure UB940. There is no 'no-boot' mode. boot from SD card and using the SDK is the only option.

Regards,

Mayank

0 Mohamed SASSI over 3 years ago in reply to Mayank Mangla

Intellectual 280 points

Hi Mayank,

The idea is generating some patterns (colors bars for example using USB2ANY for the moment) that go to the deserializer and then to the J721E EVM via the CSI2 interface and finally display the input in a screen using one of the interfaces (HDMI, DP). So, to sum up:

Computer --> USB2ANY --> Deserializer (UB940) --> J721E EVM --> Screen

You said there is a demo where I can edit the configuration of the UB960, what demo you are talking about? I think it handles capturing data not displaying it in the screen, am I right? What do you suggest in this case?
Should I use the PSDKL or the PSDKR is sufficient?
Do you think I can use a loop in the future, I mean generating patterns (videos, images) using the J721E EVM instead of the computer through USB2ANY? ( J721E EVM -->Deserializer (UB940) --> J721E EVM --> Screen)

Regards,
Mohamed

0 Mayank Mangla over 3 years ago in reply to Mohamed SASSI

TI__Mastermind 24525 points

Hello Mohamed,

This flow is not supported as-is, but you may modify the sensor driver to do it. SDK 7.1 and later supports a UB96xx test pattern. In this case, Jacinto programs UB96x chip. If UB96x is controlled by PC, you may disable the configuration code in J7 sensor driver and the rest should work with minimal changes.

Regards,

Mayank

0 Mohamed SASSI over 3 years ago in reply to Mayank Mangla

Intellectual 280 points

Hello Mayank,

I am trying to make the UB940 generate patterns(Colors bars for example) but in vain. I am editing the file in <SDK_PATH>/imaging/sensor_drv/src/ub9xx_yuv_test_pattern/ub9xx_testpat_serdes_config.h to replace the configuration of UB960 with the configuration of the UB940.

It looks like this:

ub9xx_testpat_serdes_config.h

Regards,
Mohamed

0 Casey McCrea over 3 years ago in reply to Mohamed SASSI

TI__Guru** 103215 points

Mohamed,

960 and 940 do not use the same reg configuration for PATGEN. Please reference the following app note for steps to configure PATGEN using DS90Ux94x-Q1 or DS90Ux92x-Q1 devices: https://www.ti.com/lit/pdf/snla132

0 Mohamed SASSI over 3 years ago in reply to Casey McCrea

Intellectual 280 points

Hello Casey,

I am using the single_cam demo with the ub9xx_yuv_test_pattern. I replaced the configuration of the 960 with the 940's configuration. For the pattern generation, the Analog LaunchPAD must be sufficient I guess.

I managed to display some patterns but the color bars are not displayed correctly as you can see in the following picture.

The other colors seem to be displayed correctly:

Where do you think the problem is coming from?

The configuration of the UH940 is as following:

7750.UH940_Config.txt

Register Display - ALP Nano 1 - DS90UH940, Connector 1

Register	Data	Name
0x0000	0x58	I2C Device ID
0x0001	0x04	Reset
0x0002	0x00	General Configuration 0
0x0003	0xF8	General Configuration 1
0x0004	0xFE	BCC Watchdog Control
0x0005	0x1E	I2C Control 1
0x0006	0x00	I2C Control 2
0x0007	0x00	REMOTE ID
0x0008	0x00	SlaveID[0]
0x0009	0x00	SlaveID[1]
0x000A	0x00	SlaveID[2]
0x000B	0x00	SlaveID[3]
0x000C	0x00	SlaveID[4]
0x000D	0x00	SlaveID[5]
0x000E	0x00	SlaveID[6]
0x000F	0x00	SlaveID[7]
0x0010	0x00	SlaveAlias[0]
0x0011	0x00	SlaveAlias[1]
0x0012	0x00	SlaveAlias[2]
0x0013	0x00	SlaveAlias[3]
0x0014	0x00	SlaveAlias[4]
0x0015	0x00	SlaveAlias[5]
0x0016	0x00	SlaveAlias[6]
0x0017	0x00	SlaveAlias[7]
0x0018	0x00	MAILBOX_18
0x0019	0x01	MAILBOX_19
0x001A	0x00	GPIO[9] and Global GPIO Config
0x001B	0x00	Frequency Counter
0x001C	0x22	General Status
0x001D	0x40	GPIO0 Config
0x001E	0x00	GPIO1_2 Config
0x001F	0x00	GPIO_3 Config
0x0020	0x00	GPIO_5_6 Config
0x0021	0x00	GPIO_7_8 Config
0x0022	0x00	Datapath Control
0x0023	0x20	RX Mode Status
0x0024	0x08	BIST Control
0x0025	0x00	BIST ERROR COUNT
0x0026	0x83	SCL High Time
0x0027	0x84	SCL Low Time
0x0028	0x20	Datapath Control 2
0x0029	0x00	Reserved
0x002A	0x00	Reserved
0x002B	0x00	I2S Control
0x002C	0x00	Reserved
0x002D	0x00	Reserved
0x002E	0x00	PCLK Test Mode
0x002F	0x00	Reserved
0x0030	0x00	Reserved
0x0031	0x00	Reserved
0x0032	0x90	Reserved
0x0033	0x25	Reserved
0x0034	0x01	DUAL_RX_CTL
0x0035	0x00	AEQ TEST
0x0036	0x00	Reserved
0x0037	0x89	MODE_SEL
0x0038	0x00	Reserved
0x0039	0x00	Reserved
0x003A	0x00	I2S_DIVSEL
0x003B	0x01	Reserved
0x003C	0x20	Reserved
0x003D	0xC0	Reserved
0x003E	0x23	Reserved
0x003F	0x00	Reserved
0x0040	0x43	Reserved
0x0041	0x03	LINK ERROR COUNT
0x0042	0x03	Reserved
0x0043	0x00	HSCC_CONTROL
0x0044	0x60	ADAPTIVE EQ BYPASS
0x0045	0x88	ADAPTIVE EQ MIN MAX
0x0046	0x00	Reserved
0x0047	0x00	Reserved
0x0048	0x0F	Reserved
0x0049	0x00	Reserved
0x004A	0x00	Reserved
0x004B	0x08	Reserved
0x004C	0x00	Reserved
0x004D	0x00	Reserved
0x004E	0x63	Reserved
0x004F	0x00	Reserved
0x0050	0x03	Reserved
0x0051	0x10	Reserved
0x0052	0x00	areg12_2
0x0053	0x01	Reserved
0x0054	0x80	Reserved
0x0055	0x00	Reserved
0x0056	0x00	areg12_6
0x0057	0x00	areg12a_f
0x0059	0x7F	Reserved
0x005A	0x20	Reserved
0x005B	0x20	Reserved
0x005C	0x00	Reserved
0x005D	0x00	Reserved
0x005F	0x00	Reserved
0x0060	0x00	Reserved
0x0061	0x00	Reserved
0x0062	0x00	Reserved
0x0063	0x00	Reserved
0x0064	0x40	PGCTL
0x0065	0x04	PGCFG
0x0066	0x03	PGIA
0x0067	0x02	PGID
0x0068	0x30	PGDBG
0x0069	0x00	PGTSTDAT
0x006A	0x02	CSICFG0
0x006B	0x50	CSICFG1
0x006C	0x13	CSIIA
0x006D	0x3F	CSIID
0x006E	0x00	GPI Pin Status 1
0x006F	0x00	GPI Pin Status 2
0x0070	0x00	Reserved
0x0071	0x00	Reserved
0x0072	0x00	Reserved
0x0073	0x07	Reserved
0x0074	0x07	Reserved
0x0075	0x08	Reserved
0x0076	0x00	Reserved
0x0077	0x00	Reserved
0x0078	0x00	Reserved
0x0079	0x00	Reserved
0x007A	0x00	Reserved
0x007B	0x00	Reserved
0x007C	0x02	Reserved
0x0080	0x72	RX_BKSV0
0x0081	0x52	RX_BKSV1
0x0082	0x3A	RX_BKSV2
0x0083	0x56	RX_BKSV3
0x0084	0xAB	RX_BKSV4
0x0090	0x00	TX_KSV0
0x0091	0x00	TX_KSV1
0x0092	0x00	TX_KSV2
0x0093	0x00	TX_KSV3
0x0094	0x00	TX_KSV4
0x0098	0x00	Reserved
0x0099	0x00	Reserved
0x009A	0x00	Reserved
0x009B	0x00	Reserved
0x009C	0x00	Reserved
0x009D	0x00	Reserved
0x009E	0x00	Reserved
0x009F	0x00	Reserved
0x00A1	0x00	Reserved
0x00A2	0x0D	Reserved
0x00C0	0x00	HDCP_DBG
0x00C1	0x00	HDCP_DBG2
0x00C4	0x00	HDCP_STS
0x00C5	0x00	Reserved
0x00C8	0xC0	Reserved
0x00C9	0x00	NVM_DATA
KSV_FIFO_DATA
0x00CA	0x00	NVM_ADDR0
KSV_FIFO_ADDR0
0x00CB	0x00	NVM_ADDR1
KSV_FIFO_ADDR1
0x00CC	0x00	Reserved
0x00E0	0x00	RPTR_TX0
0x00E1	0x00	RPTR_TX1
0x00E2	0x00	RPTR_TX2
0x00E3	0x00	RPTR_TX3
0x00E8	0x00	Reserved
0x00E9	0x00	Reserved
0x00EA	0x00	Reserved
0x00F0	0x5F	HDCP_RX_ID0
0x00F1	0x55	HDCP_RX_ID1
0x00F2	0x48	HDCP_RX_ID2
0x00F3	0x39	HDCP_RX_ID3
0x00F4	0x34	HDCP_RX_ID4
0x00F5	0x30	HDCP_RX_ID5
0x00F6	0x00	Reserved
0x00F8	0x00	Reserved
0x00F9	0x00	Reserved
################# PATGEN Registers #####################
Register Display - ALP Nano 1 - DS90UH940, Connector 1

Register	Data	Name
0x0000	0x00	PGRS
0x0001	0x00	PGGS
0x0002	0x00	PGBS
0x0003	0x02	PGCDC1
0x0004	0x70	PGTFS1
0x0005	0xE6	PGTFS2
0x0006	0x2E	PCTFS3
0x0007	0x00	PGAFS1
0x0008	0x05	PGAFS2
0x0009	0x2D	PGAFS3
0x000A	0x50	PGHSW
0x000B	0x05	PGVSW
0x000C	0xD8	PGHBP
0x000D	0x16	PGVBP
0x000E	0x00	PBSC
0x000F	0x1E	PGFT
0x0010	0x0E	PGTSC
0x0011	0x21	PGTSO1
0x0012	0x43	PGTSO2
0x0013	0x65	PGTSO3
0x0014	0x87	PGTSO4
0x0015	0xA9	PGTSO5
0x0016	0xCB	PGTSO6
0x0017	0xED	PGTSO7
0x0018	0x0F	PGTSO8
0x0019	0x00	PGBE
0x001A	0x01	PGCDC2
################ CSI Registers ########################
Register Display - ALP Nano 1 - DS90UH940, Connector 1

Register	Data	Name
0x0009	0x00	RAW_ALIGN
0x0013	0x3F	CSI_EN_PORT0
0x0014	0x3F	CSI_EN_PORT1
0x0016	0x02	CSIPASS
0x002E	0x00	CSI_VC_ID

Regards,
Mohamed

0 Casey McCrea over 3 years ago in reply to Mohamed SASSI

TI__Guru** 103215 points

Hello Mohamed,

What video timing is your display panel expecting? Also in the reg dump that you provided, PATGEN is actually disabled in register 0x64[0]

Best Regards,

Casey

0 Mohamed SASSI over 3 years ago in reply to Casey McCrea

Intellectual 280 points

Hi Casey,

The display panel is expecting the 1080p 60Hz resolution.
About the reg dump, I am using the ALP GUI to enable/disable the PATGEN. So, I don't think this is the problem since I am getting patterns displayed in the screen.

Also, do you know how to disable the M/N divider?

Best Regards,

Mohamed

0 Casey McCrea over 3 years ago in reply to Mohamed SASSI

TI__Guru** 103215 points

Hello Mohamed,

940 will not be able to generate exactly 1080p timing with internal clock since the internal clock is not tightly controlled and does not have exactly the right base frequency to meet 148.5MHz PCLK. That may be part of the issue here, but please try the following. Change the PGCDC1 register to 0x01 in your PATGEN configuration to set M = 1. That should net you roughly 140MHz PCLK frequency which may give better results. If you want to generate a more accurate PCLK frequency you need to connect a serializer partner and provide 148.5MHz PCLK from the serializer to the deserializer and then use external clock mode for the PATGEN in 940

Best Regards,

Casey

0 Mohamed SASSI over 3 years ago in reply to Casey McCrea

Intellectual 280 points

Dear Casey,

Thanks for your answer. The idea of using a serializer connected to the UH940 seems good. I will try it.

About the internal timing, when you said editing the M value of the M/N divider, I think you meant the PGCDC2 register ( the PGCDC1 is responsible of the N value).

Another thing, according the PATGEN documentation in the link that you gave me before: https://www.ti.com/lit/pdf/snla132 . For the PGCDC1 register (N value) The values 0x00 and 0x01 are reserved and cannot be used. Does this mean that the PCLK will be divided by 2 in best cases when we use the internal timing ?

Best Regards,
Mohamed

0 Mohamed SASSI over 3 years ago in reply to Mohamed SASSI

Intellectual 280 points

Also,
Do you think the difference between the frequencies in the serializer and the deserializer normal? If not, it's due to what ?

Thank you.

Best Regards,
Mohamed

0 Casey McCrea over 3 years ago in reply to Mohamed SASSI

TI__Guru** 103215 points

Hello Mohamed,

Sorry my mistake on the N value. Yes you are right it can not be 0 or 1. I would still recommend using the SER side PATGEN to enable a more granular frequency for the PCLK.

As for the difference between SER/DES reported PCLK, the result is expected. The frequency detection circuit is not designed to be highly accurate and typically the SER side reports a more accurate frequency compared with the DES.

Best Regards,

Casey

0 Mohamed SASSI over 3 years ago in reply to Casey McCrea

Intellectual 280 points

Hello Casey,

I connected the UH949 EVM to the the UH940 EVM, the problem is still there.
Is there any software modification I should be aware of. I am currently using vision_apps and I replaced the configuration of UB960 with the UH940 in the ub9xx_testpat_serdes_config.h in the following path: <SDK_PATH>/imaging/sensor_drv/src/ub9xx_yuv_test_pattern.

Best Regards,
Mohamed

0 Casey McCrea over 3 years ago in reply to Mohamed SASSI

TI__Guru** 103215 points

Hello Mohamed,

Can you share the configuration you used here for 949/940? Does 949 have a video source? Is the 949 configured for PATGEN? Please share the ALP info tab too. In the screenshot from before it looks like you are using ~130MHz PCLK on the 949 side?

Best Regards,

Casey

0 Mohamed SASSI over 3 years ago in reply to Casey McCrea

Intellectual 280 points

Hello Casey,

Please find the configuration in the following files:

949 configuration (both main registers and patgen registers):

949_Configuration.txt

Register Display - ALP Nano 1 - DS90UH949, Connector 1

Register	Data	Name
0x0000	0x18	I2C Device ID
0x0001	0x00	Reset
0x0003	0xDA	General Configuration
0x0004	0x80	Mode Select
0x0005	0x00	I2C Master Config
0x0006	0x58	DES ID
0x0007	0x58	SlaveID[0]
0x0008	0xB0	SlaveAlias[0]
0x0009	0x00	Reserved
0x000A	0x2A	Back Channel CRC Errors
0x000B	0x01	Back Channel CRC Errors
0x000C	0x03	General Status
0x000D	0x10	GPIO[0] Config
0x000E	0x00	GPIO[1] and GPIO[2] Config
0x000F	0x00	GPIO[3] Config
0x0010	0x00	GPIO[5] and GPIO[6] Config
0x0011	0x00	GPIO[7] and GPIO[8] Config
0x0012	0x00	Datapath Control
0x0013	0x88	General Purpose Control
0x0014	0x00	BIST and DOPL Control
0x0015	0x01	I2C_VSELECT
0x0016	0xFE	BCC Watchdog Control
0x0017	0x1E	I2C Control
0x0018	0x7F	SCL High Time
0x0019	0x7F	SCL Low Time
0x001A	0x01	Datapath Control 2
0x001B	0x00	BIST BC Error Count
0x001C	0x00	GPI Pin Status 1
0x001D	0x00	GPI Pin Status 2
0x001E	0x05	TX_PORT_SEL
0x001F	0x00	Frequency Counter
0x0020	0x0B	Deserializer Capabilities 1
0x0021	0x00	Deserializer Capabilities 2
0x0022	0x25	Reserved
0x0023	0x00	Reserved
0x0024	0x00	Reserved
0x0025	0x00	Reserved
0x0026	0x00	Link Detect Control
0x0027	0x00	Reserved
0x0028	0x01	Reserved
0x0029	0x20	Reserved
0x002A	0x20	Reserved
0x002B	0x90	Reserved
0x002C	0x00	Reserved
0x0030	0x00	SCLK_CTRL
0x0031	0x00	AUDIO_CTS0
0x0032	0x00	AUDIO_CTS1
0x0033	0x00	AUDIO_CTS2
0x0034	0x00	AUDIO_N0
0x0035	0x00	AUDIO_N1
0x0036	0x00	AUDIO_N2_COEFF
0x0037	0x00	CLK_CLEAN_STS
0x0038	0x00	Reserved
0x0039	0x00	Reserved
0x003A	0x00	Reserved
0x003B	0x00	Reserved
0x003C	0x00	Reserved
0x003D	0x00	Reserved
0x003E	0x00	Reserved
0x003F	0x00	Reserved
0x0040	0x14	Reserved
0x0041	0x55	Reserved
0x0042	0x00	Reserved
0x0043	0x00	Reserved
0x0044	0x80	Reserved
0x0045	0x00	Reserved
0x0046	0x00	Reserved
0x0047	0x00	Reserved
0x0048	0x01	APB_CTL
0x0049	0x68	APB_ADR0
0x004A	0x01	APB_ADR1
0x004B	0x00	APB_DATA0
0x004C	0x00	APB_DATA1
0x004D	0x00	APB_DATA2
0x004E	0x00	APB_DATA3
0x004F	0x00	BRIDGE_CTL
0x0050	0x17	BRIDGE_STS
0x0051	0xA1	EDID_ID
0x0052	0x1E	EDID_CFG0
0x0053	0x00	EDID_CFG1
0x0054	0x20	BRIDGE_CFG
0x0055	0x0C	AUDIO_CFG
0x0056	0x00	Reserved
0x0057	0x00	Reserved
0x0058	0x00	Reserved
0x0059	0x00	Reserved
0x005A	0xC1	DUAL_STS
0x005B	0x22	DUAL_CTL1
0x005C	0x02	DUAL_CTL2
0x005D	0x06	FREQ_LOW
0x005E	0x44	FREQ_HIGH
0x005F	0x94	HDMI_FREQ
0x0060	0x22	SPI_TIMING1
0x0061	0x02	SPI_TIMING2
0x0062	0x00	SPI_CONFIG
0x0064	0x21	PGCTL
0x0065	0x04	PGCFG
0x0066	0x03	PGIA
0x0067	0x1B	PGID
0x0068	0x30	Reserved
0x0069	0x10	Reserved
0x006A	0x00	Reserved
0x006B	0x00	Reserved
0x006C	0x00	Reserved
0x0070	0x00	SlaveID[1]
0x0071	0x00	SlaveID[2]
0x0072	0x00	SlaveID[3]
0x0073	0x00	SlaveID[4]
0x0074	0x00	SlaveID[5]
0x0075	0x00	SlaveID[6]
0x0076	0x00	SlaveID[7]
0x0077	0x00	SlaveAlias[1]
0x0078	0x00	SlaveAlias[2]
0x0079	0x00	SlaveAlias[3]
0x007A	0x00	SlaveAlias[4]
0x007B	0x00	SlaveAlias[5]
0x007C	0x00	SlaveAlias[6]
0x007D	0x00	SlaveAlias[7]
0x0080	0x00	RX_BKSV0
0x0081	0x00	RX_BKSV1
0x0082	0x00	RX_BKSV2
0x0083	0x00	RX_BKSV3
0x0084	0x00	RX_BKSV4
0x0090	0xDF	TX_KSV0
0x0091	0x8E	TX_KSV1
0x0092	0xCC	TX_KSV2
0x0093	0xA7	TX_KSV3
0x0094	0xEF	TX_KSV4
0x0098	0x00	Reserved
0x0099	0x00	Reserved
0x009A	0x00	Reserved
0x009B	0x00	Reserved
0x009C	0x00	Reserved
0x009D	0x00	Reserved
0x009E	0x00	Reserved
0x009F	0x00	Reserved
0x00A0	0x00	RX_BCAPS
0x00A1	0x00	RX_BSTATUS0
0x00A2	0x00	RX_BSTATUS1
0x00A3	0x00	KSV_FIFO
0x00C0	0x00	HDCP_DBG
0x00C1	0x00	Reserved
0x00C2	0xA8	HDCP_CFG
0x00C3	0x00	HDCP_CTL
0x00C4	0x28	HDCP_STS
0x00C5	0x00	Reserved
0x00C6	0x00	HDCP_ICR
0x00C7	0x60	HDCP_ISR
0x00C8	0x40	NVM_CTL
0x00C9	0x00	Reserved
0x00CA	0x00	Reserved
0x00CB	0x00	Reserved
0x00CC	0x00	Reserved
0x00CE	0xFF	BLUE_SCREEN
0x00D0	0x00	IND_STS
0x00D1	0x00	IND_SAR
0x00D2	0x00	IND_OAR
0x00D3	0x00	IND_DATA
0x00E0	0x00	HDCP_DBG_ALIAS
0x00E1	0x00	Reserved
0x00E2	0xA8	HDCP_CFG_ALIAS
0x00E3	0x00	HDCP_CTL_ALIAS
0x00E4	0x28	HDCP_STS_ALIAS
0x00E5	0x08	Reserved
0x00E6	0x00	HDCP_ICR_ALIAS
0x00E7	0x00	HDCP_ISR_ALIAS
0x00F0	0x5F	HDCP_TX_ID0
0x00F1	0x55	HDCP_TX_ID1
0x00F2	0x48	HDCP_TX_ID2
0x00F3	0x39	HDCP_TX_ID3
0x00F4	0x34	HDCP_TX_ID4
0x00F5	0x39	HDCP_TX_ID5
0x00F6	0x00	Reserved
0x00F8	0x00	Reserved
0x00F9	0x00	Reserved

############### PATGEN Registers ##################
Register Display - ALP Nano 1 - DS90UH949, Connector 1

Register	Data	Name
0x0000	0x00	PGRS
0x0001	0x00	PGGS
0x0002	0x00	PGBS
0x0003	0x1B	PGCDC1
0x0004	0x98	PGTFS1
0x0005	0x58	PGTFS2
0x0006	0x46	PCTFS3
0x0007	0x80	PGAFS1
0x0008	0x87	PGAFS2
0x0009	0x43	PGAFS3
0x000A	0x2C	PGHSW
0x000B	0x05	PGVSW
0x000C	0x94	PGHBP
0x000D	0x24	PGVBP
0x000E	0x02	PBSC
0x000F	0x1E	PGFT
0x0010	0x0E	PGTSC
0x0011	0x21	PGTSO1
0x0012	0x43	PGTSO2
0x0013	0x65	PGTSO3
0x0014	0x87	PGTSO4
0x0015	0xA9	PGTSO5
0x0016	0xCB	PGTSO6
0x0017	0xED	PGTSO7
0x0018	0x0F	PGTSO8
0x0019	0x00	PGBE
0x001A	0x05	PGCDC2

940 configuration (remote registers):

940_Configuration.txt

Register Display - ALP Nano 1 - DS90UH940, Connector 1

Register	Data	Name
0x0000	0x58	I2C Device ID
0x0001	0x04	Reset
0x0002	0x00	General Configuration 0
0x0003	0xF0	General Configuration 1
0x0004	0xFE	BCC Watchdog Control
0x0005	0x1E	I2C Control 1
0x0006	0x00	I2C Control 2
0x0007	0x18	REMOTE ID
0x0008	0x00	SlaveID[0]
0x0009	0x00	SlaveID[1]
0x000A	0x00	SlaveID[2]
0x000B	0x00	SlaveID[3]
0x000C	0x00	SlaveID[4]
0x000D	0x00	SlaveID[5]
0x000E	0x00	SlaveID[6]
0x000F	0x00	SlaveID[7]
0x0010	0x00	SlaveAlias[0]
0x0011	0x00	SlaveAlias[1]
0x0012	0x00	SlaveAlias[2]
0x0013	0x00	SlaveAlias[3]
0x0014	0x00	SlaveAlias[4]
0x0015	0x00	SlaveAlias[5]
0x0016	0x00	SlaveAlias[6]
0x0017	0x00	SlaveAlias[7]
0x0018	0x00	MAILBOX_18
0x0019	0x01	MAILBOX_19
0x001A	0x00	GPIO[9] and Global GPIO Config
0x001B	0x00	Frequency Counter
0x001C	0x3B	General Status
0x001D	0x40	GPIO0 Config
0x001E	0x00	GPIO1_2 Config
0x001F	0x00	GPIO_3 Config
0x0020	0x00	GPIO_5_6 Config
0x0021	0x00	GPIO_7_8 Config
0x0022	0x00	Datapath Control
0x0023	0x20	RX Mode Status
0x0024	0x08	BIST Control
0x0025	0x00	BIST ERROR COUNT
0x0026	0x14	SCL High Time
0x0027	0x26	SCL Low Time
0x0028	0x11	Datapath Control 2
0x0029	0x00	Reserved
0x002A	0x00	Reserved
0x002B	0x04	I2S Control
0x002C	0x00	Reserved
0x002D	0x00	Reserved
0x002E	0x00	PCLK Test Mode
0x002F	0x00	Reserved
0x0030	0x00	Reserved
0x0031	0x00	Reserved
0x0032	0x90	Reserved
0x0033	0x25	Reserved
0x0034	0x09	DUAL_RX_CTL
0x0035	0x00	AEQ TEST
0x0036	0x00	Reserved
0x0037	0x89	MODE_SEL
0x0038	0x00	Reserved
0x0039	0x00	Reserved
0x003A	0x00	I2S_DIVSEL
0x003B	0x37	Reserved
0x003C	0x20	Reserved
0x003D	0xC0	Reserved
0x003E	0x23	Reserved
0x003F	0x00	Reserved
0x0040	0x43	Reserved
0x0041	0x03	LINK ERROR COUNT
0x0042	0x03	Reserved
0x0043	0x00	HSCC_CONTROL
0x0044	0x60	ADAPTIVE EQ BYPASS
0x0045	0x88	ADAPTIVE EQ MIN MAX
0x0046	0x00	Reserved
0x0047	0x00	Reserved
0x0048	0x0F	Reserved
0x0049	0x00	Reserved
0x004A	0x00	Reserved
0x004B	0x08	Reserved
0x004C	0x00	Reserved
0x004D	0x00	Reserved
0x004E	0x63	Reserved
0x004F	0x00	Reserved
0x0050	0x03	Reserved
0x0051	0x10	Reserved
0x0052	0x00	areg12_2
0x0053	0x01	Reserved
0x0054	0x80	Reserved
0x0055	0x00	Reserved
0x0056	0x00	areg12_6
0x0057	0x00	areg12a_f
0x0059	0x7F	Reserved
0x005A	0x20	Reserved
0x005B	0x20	Reserved
0x005C	0x00	Reserved
0x005D	0x00	Reserved
0x005F	0x00	Reserved
0x0060	0x00	Reserved
0x0061	0x00	Reserved
0x0062	0x00	Reserved
0x0063	0x00	Reserved
0x0064	0x10	PGCTL
0x0065	0x08	PGCFG
0x0066	0x00	PGIA
0x0067	0x00	PGID
0x0068	0x00	PGDBG
0x0069	0x00	PGTSTDAT
0x006A	0x02	CSICFG0
0x006B	0x50	CSICFG1
0x006C	0x00	CSIIA
0x006D	0x07	CSIID
0x006E	0x00	GPI Pin Status 1
0x006F	0x00	GPI Pin Status 2
0x0070	0x00	Reserved
0x0071	0x00	Reserved
0x0072	0x00	Reserved
0x0073	0x07	Reserved
0x0074	0x07	Reserved
0x0075	0x08	Reserved
0x0076	0x00	Reserved
0x0077	0x00	Reserved
0x0078	0x00	Reserved
0x0079	0x00	Reserved
0x007A	0x00	Reserved
0x007B	0x6D	Reserved
0x007C	0x02	Reserved
0x0080	0x72	RX_BKSV0
0x0081	0x52	RX_BKSV1
0x0082	0x3A	RX_BKSV2
0x0083	0x56	RX_BKSV3
0x0084	0xAB	RX_BKSV4
0x0090	0x00	TX_KSV0
0x0091	0x00	TX_KSV1
0x0092	0x00	TX_KSV2
0x0093	0x00	TX_KSV3
0x0094	0x00	TX_KSV4
0x0098	0x00	Reserved
0x0099	0x00	Reserved
0x009A	0x00	Reserved
0x009B	0x00	Reserved
0x009C	0x00	Reserved
0x009D	0x00	Reserved
0x009E	0x00	Reserved
0x009F	0x00	Reserved
0x00A1	0x00	Reserved
0x00A2	0x0D	Reserved
0x00C0	0x00	HDCP_DBG
0x00C1	0x00	HDCP_DBG2
0x00C4	0x00	HDCP_STS
0x00C5	0x00	Reserved
0x00C8	0xC0	Reserved
0x00C9	0x00	NVM_DATA
KSV_FIFO_DATA
0x00CA	0x00	NVM_ADDR0
KSV_FIFO_ADDR0
0x00CB	0x00	NVM_ADDR1
KSV_FIFO_ADDR1
0x00CC	0x00	Reserved
0x00E0	0x00	RPTR_TX0
0x00E1	0x00	RPTR_TX1
0x00E2	0x00	RPTR_TX2
0x00E3	0x00	RPTR_TX3
0x00E8	0x00	Reserved
0x00E9	0x00	Reserved
0x00EA	0x00	Reserved
0x00F0	0x5F	HDCP_RX_ID0
0x00F1	0x55	HDCP_RX_ID1
0x00F2	0x48	HDCP_RX_ID2
0x00F3	0x39	HDCP_RX_ID3
0x00F4	0x34	HDCP_RX_ID4
0x00F5	0x30	HDCP_RX_ID5
0x00F6	0x00	Reserved
0x00F8	0x00	Reserved
0x00F9	0x00	Reserved

Please note that the 949 is configured for PATGEN as you can see in the following picture:

For the frequencies, I tried both the ≈130MHz from the 949 side ( which gives me ≈ 148MHz in the 940 side according to ALP) and the ≈148MHz as you can see in the picture. None of them worked.

Also, I tried to connect the HDMI Input of the 949 to my computer's HDMI output. The image is displayed correctly but only 1/4 of my computer's screen.

Best Regards,

Mohamed

0 Casey McCrea over 3 years ago in reply to Mohamed SASSI

TI__Guru** 103215 points

Hello Mohamed,

It sounds like the issue is related to the SoC configuration, not the FPD-Link configuration so I'm moving your question to the processors forum for additional help

Best Regards,

Casey

0 Brijesh Jadav over 3 years ago in reply to Casey McCrea

TI__Guru**** 426695 points

Hello Mohamed,

I am sorry i am not getting what is the issue? Can you please summarize?

Are you now able to capture image from the ub940/949? Is it just the issue in the display? Could you pls help to understand?

Regards,

Brijesh

Processors

Processors forum

TDA4VM: Data acquisition from UB940