AM4378: System freezes with Linux rootfs on eMMC

No similar issues reported.

The series resistor, R194, needs to be close to the AM437x pin to resolve signal distortion issues since the clock output is looped back into the AM437x device, and signal distortion on the source end of the clock signal can produce glitches on the internal looped back clock. How much etch length is used to connect R194 to the AM437x pin? 

The 47 ohm series resistors may be attenuating high-frequency portions of the signal which will reduce rise/fall time and erode timing margin. Have you tried to reduce the impedance of these resistors? 

Did the system designer perform timing analysis of MMC0 signal paths using actual PCB delays along with datasheet timing requirements and switching characteristics of AM437x and attached device?  If not, the signals may be violating setup and/or hold timing requirements of the AM437x or attached device.

Can you perform a series of read write tests using known data patterns when rootfs is loaded in RAM. If so, you may be able to debug your issue by comparing actual data patterns to expected data patterns.

Regards,
Paul

Hi Paul,

Thanks for your reply.
Here are answers from customer to your questions/comments.

- R194 is near eMMC device and ~68mm from AM437x pin. Is this problematic?
- Customer tested 0, 22, 47 and 91 ohm resistors for evaluation and decided 47 ohm as 0 and 22 ohm showed much higher overshoot/undershoot.
- Customer tested signal timing measurements on the board and confirm these results met AC timings of AM437x. These results were also checked by eMMC supplier and confirmed fine.
- Customer is considering to perform read/write test you proposed.

Thanks and regards,
Koichiro Tashiro

The 68mm of etch connecting the AM437x clock pin and series resistor may be contributing to the problem. The input buffer which loops the clock back into the device from the output buffer will see a mid-supply voltage step when the output signal transitions. The step occurs because the AM437x pin is effectively connected to the output of a voltage divider where the output buffer impedance is R1 and the characteristic impedance of the signal trace is R2. For example, the voltage step would be Vstep = VDD (Trace impedance / (Output impedance + Trace impedance)). The first voltage step that is applied to the input buffer will be present for about 890ps in their case, which is the time it takes for the signal to propagate down 68mm of trace to the series resistor where the first impedance discontinuity reflection returns back on the same 68mm of trace. So the step will be present for two times the trace delay. At this point the signal will transition to another voltage step which is present until the signal propagates to the eMMC device where another reflection returns. This step will be present for two times the total trace delay from AM437x to the eMMC device.

The first step is the most problematic because its potential may be close to the input buffer switching threshold. If this voltage step is too close to the switching threshold the input buffer may see a non-monotonic transition due to electrical noise in the system. If this occurs the looped back clock can be glitched and unpredictable things will happen in the logic since this glitch is effectively over-clocking the logic. You significantly reduce the chance of this occurring by keeping the trace length between the AM437x pin and series resistor very short.

The longer duration second step is less likely to be a problem since the series resistor allows the next step to reach a higher voltage that is above the switching threshold.

Regards,
Paul