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66AK2G12: questions about (1)Scrachpad Registers (2) SPI Boot (3) DDR3L IO coherency

user3788809
Intellectual 900 points
Part Number: 66AK2G12

Hi,

could you tell me following background knowledge? Could you please explain?

(1)

What's "scratchpad use"? (cf. 5.1.3.1.10 Scrachpad Registers in TRM)

(I don't know what scratchpad use is in the first place.)

(2)

As for Boot mode configuration by SPI,

what is the difference between "SPI without PLL Boot Device Configuration" and "SPI with PLL Boot Device Configuration"?

(cf. Figure 4-7 and Figure 4-8 in TRM)

Although I am supposed to use SPI Flash memory boot, I don't know how BOOTMODE Pin should be set

becasue I don't know the difference between "SPI without PLL Boot Device Configuration" and "SPI with PLL Boot Device Configuration."

(3)

As for Device Memory Map for DDR_0_DATA in TRM,

what is IO coherency? (Could you please explain the difference between "2G area(00 8000 0000--00 FFFF FFFF)" and "8G area(08 0000 0000--09 FFFF FFFF)"?)

Regards.

  • 0
    TI__Guru* 85990 points

    Scratchpad registers are general purpose registers used for user-defined information.  They are located in the ALWAYS_ON power domain, so they can be used to store information for modules in other power domains even when other power domains have been turned off.    

    For SPI boot mode, the difference is just whether or not the MAIN_PLL is programmed to a frequency indicated by the device_speed field in the efuse_bootrom register.  If the PLL isn't programmed, the bypass frequency is used

    Coherency is an indication of whether or not all initiators in the system will see the same contents in memory.  Sometimes coherency is not maintained if an initiator (for example, the A15) uses cache which does not update the external memory on every access.  The operation of coherency by the MSMC is described in section 7.1.3.9.  The 2G area which does not have IO coherency is indicated in the memory map.  When the initiators access this portion of memory, coherency is not guaranteed between the A15 and other initiators.  Since access to the 8G area goes thru the MSMC, coherency can be maintained across all initiators

    REgards,

    James