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TDA4VM: TDA4 PSDK 7.1 Memory Map Changes

Swapnil Nagare
Intellectual 340 points
Part Number: TDA4VM
Hello ,
We are migrating existing running application from PSDK7.0 to PSDK7.1.
With latest PSDK 7.1 memory map we faced memory linking errors on C66x as below.
--------------------------------------------------------------------------------------------------------
program will not fit into available memory. placement with alignment fails
for section ".const" size 0x15ed4c . Available memory ranges:
DDR_C66x_2 size: 0xdffc00 unused: 0x44706 max hole: 0x3ff40
--------------------------------------------------------------------------------------------------------
After comparing memory map with PSDK 7.0 it was observed that C66 memory segments sizes have been reduced by 16MB in he latest PSDK memory map.
We tried to restore the C66 memory sizes by using the 16 MB hole between C66x_2 and C7x.
The application is getting compiled but during runtime the application hangs in verify graph api.
Could you suggest what could be the reason or is there any other way we can increase C66 memory sizes?
Regard,
Swapnil N
  • 0
    TI__Genius 10355 points

    There are a few restrictions and care-about while changing memory map. Did you go over this developer note before attempting to change the memory map. The key here being that you also need to update the dtb overlay file if you are using Linux.

    https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/psdk_rtos/docs/user_guide/developer_notes_memory_map.html

    Regards,
    Shyam

  • 0 in reply to Shyam Jagannathan
    TI__Guru** 113810 points

    Customer posted more information on this thread: https://e2e.ti.com/support/processors/f/processors-forum/987039/tda4vm-tda4vm

    Copy pasting below over here:

    Hi Shyam,

    We have gone through the developer note initially . Also, we are working on qnx, not linux.
    We are migrating an application from PSDK7.0 to PSDK7.1. During this process, we have observed that there are some major memory map changes for PSDK7.1 w.r.t. qnx . This change is causing us an issue for below reasons .
    1.Kernels running on c6x have a greater memory requirement .
    This is observed when we tried to compile the application and faced the below error.
    -------------------------------------------------------------------------------------------------------------
    program will not fit into available memory. placement with alignment fails for section ".const" size 0x15ed4c . Available memory ranges: DDR_C66x_2 size: 0xdffc00 unused: 0x44706 max hole: 0x3ff40
    -------------------------------------------------------------------------------------------------------------
    To address the first issue , we tried to borrow some memory from c6x_1(2 MB) to increase the memory for c6x_2 . This helped us resolve the compilation issue , but we observed that the application hangs after the 1st frame execution .
    2. To address above hang issue, we increased the DSP stack size (This change was done in PSDK7.0 as it was a requirement for one of our algorithms . )
    But after this , we started facing compilation issues as below
    -------------------------------------------------------------------------------------------------------------
    program will not fit into available memory. placement with alignment fails for section ".text" size 0x126d00 . Available memory ranges: DDR_C66x_1 size: 0xdffc00 unused: 0xe4142 max hole: 0xdff40
    program will not fit into available memory. placement with alignment fails for section ".const" size 0x15ed4c . Available memory ranges: DDR_C66x_2 size: 0xdffc00 unused: 0x44706 max hole: 0x3ff40
    program will not fit into available memory, or the section contains a call site that requires a trampoline that can't be generated for this section. run placement with alignment fails for section ".bss:taskStackSection" size
    0x208000. Available memory ranges: DDR_C7x_1 size: 0x9fc000 unused: 0x15f55f max hole: 0x140000
    -------------------------------------------------------------------------------------------------------------
    To resolve these issues , we analysed PSDK7.1 memory map and observed that 16 MB of memory (8MB each of c6x_1 and c6x_2) was reduced but not used for any other core . Hence , we tried to increase c6x_1_ddr_size and c6x_2_ddr_size to 24 MB each (same as PSDK7.0) .
    This helped us resolve above compilation issues but our application hangs in verifyGraph().
    3.To resolve the hang issue in verifyGraph , some memory from MCU2_1 was borrowed and distributed among C6x and c7x. Memory map changes are as follows:
    1.MCU2_1 memory was reduced by 12MB (changed from 32MB to 20 MB).
    2.c6x_1 memory was increased by 2 MB  (changed from 16MB to 18 MB).
    3.c6x_2 memory was increased by 6 MB (changed from 16MB to 22 MB).
    4.c7x memory was increased by 4 MB (changed from 16MB to 20 MB).
    After these changes, the application is working fine. Kindly help us understand if the memory changes done are correct.
    Also , can you tell us if we can use the hole memory of 16 MB instead of changing the memory map of MCU2_1.

    System Memory Map for Linux+RTOS mode

    Note, this file is auto generated using PyTI_PSDK_RTOS tool

    Name Start Addr End Addr Size Attributes Description
    L2RAM_C66x_1 0x00800000 0x00837FFF 224.00 KB RWIX L2 for C66x_1
    L2RAM_C66x_2 0x00800000 0x00837FFF 224.00 KB RWIX L2 for C66x_2
    MAIN_OCRAM_MCU2_0 0x03600000 0x0361FFFF 128.00 KB RWIX Main OCRAM for MCU2_0
    MAIN_OCRAM_MCU2_1 0x03620000 0x0363FFFF 128.00 KB RWIX Main OCRAM for MCU2_1
    L2RAM_C7x_1 0x64800000 0x64877FFF 480.00 KB RWIX L2 for C7x_1
    L1RAM_C7x_1 0x64E00000 0x64E03FFF 16.00 KB RWIX L1 for C7x_1
    MSMC_MPU1 0x70000000 0x7001FFFF 128.00 KB RWIX MSMC reserved for MPU1 for ATF
    MSMC_C7x_1 0x70020000 0x707E7FFF 7.78 MB RWIX MSMC for C7x_1
    MSMC_DMSC 0x707F0000 0x707FFFFF 64.00 KB RWIX MSMC reserved for DMSC IPC
    DDR_MCU1_0_IPC 0xA0000000 0xA00FFFFF 1024.00 KB RWIX DDR for MCU1_0 for Linux IPC
    DDR_MCU1_0_RESOURCE_TABLE 0xA0100000 0xA01003FF 1024 B RWIX DDR for MCU1_0 for Linux resource table
    DDR_MCU1_0 0xA0100400 0xA0FFFFFF 15.00 MB RWIX DDR for MCU1_0 for code/data
    DDR_MCU2_0_IPC 0xA1000000 0xA10FFFFF 1024.00 KB RWIX DDR for MCU2_0 for Linux IPC
    DDR_MCU2_0_RESOURCE_TABLE 0xA1100000 0xA11003FF 1024 B RWIX DDR for MCU2_0 for Linux resource table
    DDR_MCU2_0 0xA1100400 0xA2FFFFFF 31.00 MB RWIX DDR for MCU2_0 for code/data
    DDR_MCU2_1_IPC 0xA3000000 0xA30FFFFF 1024.00 KB RWIX DDR for MCU2_1 for Linux IPC
    DDR_MCU2_1_RESOURCE_TABLE 0xA3100000 0xA31003FF 1024 B RWIX DDR for MCU2_1 for Linux resource table
    DDR_MCU2_1 0xA3100400 0xA43FFFFF 19.00 MB RWIX DDR for MCU2_1 for code/data
    DDR_MCU3_0_IPC 0xA4400000 0xA44FFFFF 1024.00 KB RWIX DDR for MCU3_0 for Linux IPC
    DDR_MCU3_0_RESOURCE_TABLE 0xA4500000 0xA45003FF 1024 B RWIX DDR for MCU3_0 for Linux resource table
    DDR_MCU3_0 0xA4500400 0xA4BFFFFF 7.00 MB RWIX DDR for MCU3_0 for code/data
    DDR_MCU3_1_IPC 0xA4C00000 0xA4CFFFFF 1024.00 KB RWIX DDR for MCU3_1 for Linux IPC
    DDR_MCU3_1_RESOURCE_TABLE 0xA4D00000 0xA4D003FF 1024 B RWIX DDR for MCU3_1 for Linux resource table
    DDR_MCU3_1 0xA4D00400 0xA53FFFFF 7.00 MB RWIX DDR for MCU3_1 for code/data
    DDR_C66x_2_IPC 0xA5400000 0xA54FFFFF 1024.00 KB RWIX DDR for C66x_2 for Linux IPC
    DDR_C66x_1_RESOURCE_TABLE 0xA5500000 0xA55003FF 1024 B RWIX DDR for C66x_1 for Linux resource table
    DDR_C66x_1_BOOT 0xA5600000 0xA56003FF 1024 B RWIX DDR for C66x_1 for boot section
    DDR_C66x_1 0xA5600400 0xA65FFFFF 16.00 MB RWIX DDR for C66x_1 for code/data
    DDR_C66x_1_IPC 0xA6600000 0xA66FFFFF 1024.00 KB RWIX DDR for C66x_1 for Linux IPC
    DDR_C66x_2_RESOURCE_TABLE 0xA6700000 0xA67003FF 1024 B RWIX DDR for C66x_2 for Linux resource table
    DDR_C66x_2_BOOT 0xA6800000 0xA68003FF 1024 B RWIX DDR for C66x_2 for boot section
    DDR_C66x_2 0xA6800400 0xA7BFFFFF 20.00 MB RWIX DDR for C66x_2 for code/data
    DDR_C7x_1_IPC 0xA7C00000 0xA7CFFFFF 1024.00 KB RWIX DDR for C7x_1 for Linux IPC
    DDR_C7x_1_RESOURCE_TABLE 0xA7D00000 0xA7D003FF 1024 B RWIX DDR for C7x_1 for Linux resource table
    DDR_C7x_1_BOOT 0xA7E00000 0xA7E003FF 1024 B RWIX DDR for C7x_1 for boot section
    DDR_C7x_1_VECS 0xA8000000 0xA8003FFF 16.00 KB RWIX DDR for C7x_1 for vecs section
    DDR_C7x_1_SECURE_VECS 0xA8200000 0xA8203FFF 16.00 KB RWIX DDR for C7x_1 for secure vecs section
    DDR_C7x_1 0xA8204000 0xA8FFFFFF 13.98 MB RWIX DDR for C7x_1 for code/data
    IPC_VRING_MEM 0xAA000000 0xABFFFFFF 32.00 MB Memory for IPC Vring's. MUST be non-cached or cache-coherent
    APP_LOG_MEM 0xAC000000 0xAC03FFFF 256.00 KB Memory for remote core logging
    TIOVX_OBJ_DESC_MEM 0xAC040000 0xADFDFFFF 31.62 MB Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent
    PCIE_QUEUE_SHARED_MEM 0xADFE0000 0xADFEFFFF 64.00 KB Memory for IPC over PCIe using shared memory. MUST be non-cached or cache-coherent
    PCIE_QUEUE_MIRROR_REMOTE_SHARED_MEM 0xADFF0000 0xADFFFFFF 64.00 KB Reserved Memory for RAT mapping of remote PCIe IPC shared memory. MUST be non-cached or cache-coherent
    DDR_SHARED_MEM 0xAE000000 0xCDFFFFFF 512.00 MB Memory for shared memory buffers in DDR
    DDR_MCU2_0_NON_CACHE 0xCE000000 0xCE00FFFF 64.00 KB RWIX DDR for MCU2_0 for non-cached heap
    DDR_MCU2_1_NON_CACHE 0xCE010000 0xD1FFFFFF 63.94 MB RWIX DDR for MCU2_1 for non-cached heap
    DDR_MCU1_0_LOCAL_HEAP 0xD2000000 0xD21FFFFF 2.00 MB RWIX DDR for MCU1_0 for local heap
    DDR_MCU1_1_LOCAL_HEAP 0xD2200000 0xD23FFFFF 2.00 MB RWIX DDR for MCU1_1 for local heap
    DDR_MCU2_0_LOCAL_HEAP 0xD2400000 0xD2BFFFFF 8.00 MB RWIX DDR for MCU2_0 for local heap
    DDR_MCU2_1_LOCAL_HEAP 0xD2C00000 0xD3BFFFFF 16.00 MB RWIX DDR for MCU2_1 for local heap
    DDR_MCU3_0_LOCAL_HEAP 0xD3C00000 0xD3DFFFFF 2.00 MB RWIX DDR for MCU3_0 for local heap
    DDR_MCU3_1_LOCAL_HEAP 0xD3E00000 0xD3FFFFFF 2.00 MB RWIX DDR for MCU3_1 for local heap
    DDR_C66X_1_LOCAL_HEAP 0xD4000000 0xD4FFFFFF 16.00 MB RWIX DDR for c66x_1 for local heap
    DDR_C66X_1_SCRATCH 0xD5000000 0xD7FFFFFF 48.00 MB RWIX DDR for c66x_1 for Scratch Memory
    DDR_C66X_2_LOCAL_HEAP 0xD8000000 0xD8FFFFFF 16.00 MB RWIX DDR for c66x_2 for local heap
    DDR_C66X_2_SCRATCH 0xD9000000 0xDBFFFFFF 48.00 MB RWIX DDR for c66x_2 for Scratch Memory
    DDR_C7X_1_LOCAL_HEAP 0xDC000000 0xEBFFFFFF 256.00 MB RWIX DDR for c7x_1 for local heap
    DDR_C7X_1_SCRATCH 0xEC000000 0xF9FFFFFF 224.00 MB RWIX DDR for c7x_1 for Scratch Memory
    TIOVX_LOG_RT_MEM 0xFA000000 0xFAFFFFFF 16.00 MB Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent
    DDR_MCU1_1_IPC 0xFB000000 0xFB0FFFFF 1024.00 KB RWIX DDR for MCU1_1 for Linux IPC
    DDR_MCU1_1_RESOURCE_TABLE 0xFB100000 0xFB1003FF 1024 B RWIX DDR for MCU1_1 for Linux resource table
    DDR_MCU1_1 0xFB100400 0xFBFFFFFF 15.00 MB RWIX DDR for MCU1_1 for code/data
  • 0 in reply to Karthik Ramanan
    TI__Genius 10355 points

    Apologize for a late reply. We have modified the memory map in the upcoming SDK 7.3 making more room in the lower 2GB part of DDR for other cores liek C66x DSP/R5Fs etc and moved C7x heap to upper 2GB section. We can incorporate these changes in SDK 7.1/7.2 as well but requires some minimum work. If you are still facing issue, please schedule a call this week and I can help modify the memory map as required.