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ECC with DDR controller in TMS320C6A8168

Mahesh Shinde
Intellectual 270 points

Hello,

I do not find anything on ECC support for DDR controller (EMIF). Does the DDR controllers (EMIF) support ECC?

If EMIF does not support ECC, how do we address the ECC? 

 

Regards,

Mahesh Shinde

 

  • 0
    TI__Mastermind 25055 points

    Mahesh,

    The GPMC module provides up to 16-Bit/512-Bytes Hardware ECC for NAND, but the DDR controller does not have any soft error recovery scheme (ECC/Parity).

    Regards,
    Marc

  • 0 in reply to MarcPyne
    Intellectual 270 points

    Hello,

    Bit surpeised to know that it does not support ECC. Interfacing DDR3 memory with the proccessor not having ECC could be a risk. How do we handle the bit error?

    Is there any support in the DDR controller to take care of bit error?

    Regards,

    Mahesh Shinde

     

  • 0 in reply to Mahesh Shinde
    Intellectual 270 points

    Hello,

     

    In addition to above question for you,

    1. Are there plans to add ECC support for DDR controller in the future versions of the silicon?

    2. Is there any other processor in the same family having ECC support on DDR controller?

    3. Could you please share your thought process on why ECC support is not provided for such a high performance processor? 

    Regards,

    Mahesh Shinde

  • 0 in reply to Mahesh Shinde
    TI__Prodigy 390 points

    From a Sitara system architect...

    "The need for ECC has been more driven by automotive market and not so much in the broader market. There is cost associated with ECC (extra memory chip and cycle penalties). There is no JEDEC spec or requirement for ECC. The ECC IP is in development now and it is a bit tricky to get correct doing it real time with all the boundary conditions. So it has taken some time to get this IP developed. There is debate long term whether ECC should go into the DRAM itself. This would be more efficient in the long run. Memory manufacturers have talked about this but I have not heard about memories

    The only method to do this for now is to run checksums on the code periodically to ensure it is correct. This chews up processor mips and also can take awhile to identify a failure."

    There is a device being planned for sampling in late 2011 that will have ECC.  Please send me (Andrew Prentice) an email separately if you'd like to know more.  

  • 0 in reply to enticedrew
    Intellectual 270 points

    Unfortunately I could not find your e-mail ID. Could you please provide me your e-mail ID?  Else, request you to please send me the preliminary info of the device on my e-mail ID mahesh.shinde@patni.com

    Regards,

    Mahesh Shinde

  • 0 in reply to enticedrew
    Prodigy 30 points

    I came across this discussion while searching for answers to the same question: how can we interface DDR2 memory to an AM335x processor with ECC. (We are considering using the Cortex-A8 processor in an Avionics display product. Reliability is extremely important.)

    This discussion stopped abruptly with a hint of some solutions being worked on. Has there been any progress on finding a way to have ECC with DDR memories?