6748 NAND Flash to EMIF connection and Boot loader

Todd F said:

There seems to be a compatibility problem between the TI Boot loader connection requirements and the DMA controller's connection requirements.  Apparently in order for the DMA controller to work, a certain connection is required, and restrictions are placed on the address range.  Therefore, my customer is concerned that the size of the DMA transfer will be restricted, but we are not sure by how much. The DMA connection also seems to be incompatible with the boot connection requirements.

Apparently TI sees a compatibility problem as well as recommends an external mux to fix it.  My question is this:

Todd,

Can you elaborate on the above statements.  I'm not aware of any recommendation regarding an external mux or problems related to boot loader NAND connection versus connection required for DMA.  Note that the connection of the NAND ALE and CLE to specific EMIF address lines has been done on a number of devices for quite a few years and I have never heard this claim until now.  So I think there may be some confusion that needs to be cleared up first.

Regards, Daniel

Daniel,

  Here is what the customer is confused by.

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As you know, we are using the TMS320C6748 in our latest design.  I'm looking for the best way to connect it to a NAND FLASH memory and I would appreciate your suggestions.  My issue concerns how to use the memory for both bootloading and normal operation.

In the EMIF User’s Guide, SPRUFL6F, the NAND interface description is given in Section 2.5.6 and connections are discussed in section 2.5.6.2, page 39.  The user guide states that “any EMIFA address lines may be used to drive the CLE and ALE signals of the NAND Flash.”

However, the NAND bootloader from the device ROM requires specific connections:  “NAND Flash should be connected to EMA_CS[3] of the EMIFA peripheral. The ALE and CLE pins of the NAND device should be connected to the EMA_A[1] and EMA_A[2] pins of the EMIFA peripheral, respectively.”  See page 19 of application report Using the TMS320C6748/C6746/C6742 Bootloader, SPRAAT2C.

The EMIF User’s Guide Section 2.5.6.5, page 40, describes the requirements for using the EDMA controller.  It states that “a linear incrementing address mode must be used. When using a linear incrementing address mode, if the CLE and ALE are driven by EM_A[2] and EM_A[1], respectively, care must be taken not to increase the address into a range that drives CLE and/or ALE high. To prevent the address from incrementing into a range that drives CLE and/or ALE high, the EDMA ACNT, BCNT, SIDX, DIDX, and synchronization type must be programmed appropriately.”  It goes on to give an example of how to configure the DMA but it does not explain the data transfer size that can be achieved with the suggested settings.

Even after looking at the EDMA user's guide, I don't fully understand the DMA operations.  It appears that if I leave the CLE and ALE lines connected to the address lines used by the bootloader, I will be limited to a pitifully small 8 bytes per transfer when accessing the NAND FLASH in normal operation.  Please recommend a method to use both the bootloader and also achieve DMA transfers of 4k bytes.

Let me know if you have any other questions about our design and desired usage.  I look forward to resolving this issue.

Todd,

If they plan to use the NAND for booting purposes, they will have to connect as the boot loader app note describes.  That will not prevent them from using the DMA as the parameters given in the EMIF user's guide will work with connections required by the boot loader.  The EDMA settings described indicate a 2-D DMA operation where the first dimension is 8 bytes wide and the second dimension will be (transferSize)/8.  The indexes for the EMIF side are such that the addresses on EMIF interface (the source for reads and the destination for writes) will cycle over the same eight adresses without toggling either A[1] or A[2]. The indexes on the memory side will provide for a continuous region of transferSize bytes.

Typically the transfer size will be 512 bytes due to the requirement to handle ECC.

I would definitely recommend they read up on the EDMA peripheral and its usage to understand the 2-D transfer and the parameters given in the EMIF user's guide.

Regards, Daniel